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Commit 817c27a1 authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: dts: imx6qdl: make pinctrl nodes board specific 



Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts.  However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected.  This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board.  It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.

The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral.  Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 682d055e

arch/arm/boot/dts/imx6q-arm2.dts

+104 −12
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 


&gpmi {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gpmi_nand_1>;

	pinctrl-0 = <&pinctrl_gpmi_nand>;

	status = "disabled"; /* gpmi nand conflicts with SD */

};
@@ -63,27 +63,119 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;



	hog {

	imx6q-arm2 {

		pinctrl_hog: hoggrp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000

			>;

		};



		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

			>;

		};



		pinctrl_gpmi_nand: gpminandgrp {

			fsl,pins = <

				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1

				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1

				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1

				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000

				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1

				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1

				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1

				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1

				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1

				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1

				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1

				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1

				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1

				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1

				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1

				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1

				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1

			>;

		};



	arm2 {

		pinctrl_usdhc3_arm2: usdhc3grp-arm2 {

		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D26__UART2_RX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D27__UART2_TX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B	0x1b0b1

				MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B	0x1b0b1

			>;

		};



		pinctrl_uart4: uart4grp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1

				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usbotg: usbotggrp {

			fsl,pins = <

				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059

				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059

				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059

				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059

			>;

		};



		pinctrl_usdhc3_cdwp: usdhc3cdwp {

			fsl,pins = <

				MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000

				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000

			>;

		};



		pinctrl_usdhc4: usdhc4grp {

			fsl,pins = <

				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059

				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059

				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059

				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059

				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059

				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059

				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059

				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059

				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059

				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059

			>;

		};

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet_2>;

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	status = "okay";

};
@@ -91,7 +183,7 @@ 
&usbotg {

	vbus-supply = <&reg_usb_otg_vbus>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbotg_1>;

	pinctrl-0 = <&pinctrl_usbotg>;

	disable-over-current;

	status = "okay";

};
@@ -101,8 +193,8 @@ 
	wp-gpios = <&gpio6 14 0>;

	vmmc-supply = <&reg_3p3v>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3_1

		     &pinctrl_usdhc3_arm2>;

	pinctrl-0 = <&pinctrl_usdhc3

		     &pinctrl_usdhc3_cdwp>;

	status = "okay";

};
@@ -110,13 +202,13 @@ 
	non-removable;

	vmmc-supply = <&reg_3p3v>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc4_1>;

	pinctrl-0 = <&pinctrl_usdhc4>;

	status = "okay";

};



&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2_2>;

	pinctrl-0 = <&pinctrl_uart2>;

	fsl,dte-mode;

	fsl,uart-has-rtscts;

	status = "okay";
@@ -124,6 +216,6 @@ 


&uart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart4_1>;

	pinctrl-0 = <&pinctrl_uart4>;

	status = "okay";

};

arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi

+74 −11
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 


&ecspi3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi3_1>;

	pinctrl-0 = <&pinctrl_ecspi3>;

	status = "okay";

	fsl,spi-num-chipselects = <1>;

	cs-gpios = <&gpio4 24 0>;
@@ -36,7 +36,7 @@ 


&i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1_1>;

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";



	eeprom@50 {
@@ -128,7 +128,7 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;



	hog {

	imx6q-phytec-pfla02 {

		pinctrl_hog: hoggrp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
@@ -136,10 +136,73 @@ 
				MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */

			>;

		};



		pinctrl_ecspi3: ecspi3grp {

			fsl,pins = <

				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1

				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1

				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1

			>;

		};



		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0

			>;

		};



		pinctrl_i2c1: i2c1grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1

				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1

			>;

		};



		pinctrl_uart4: uart4grp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1

				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usdhc2: usdhc2grp {

			fsl,pins = <

				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059

				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059

				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059

				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059

				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059

				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};



	pfla02 {

		pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {

		pinctrl_usdhc3_cdwp: usdhc3cdwp {

			fsl,pins = <

				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000

				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
@@ -150,7 +213,7 @@ 


&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet_3>;

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	phy-reset-gpios = <&gpio3 23 0>;

	status = "disabled";
@@ -158,13 +221,13 @@ 


&uart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart4_1>;

	pinctrl-0 = <&pinctrl_uart4>;

	status = "disabled";

};



&usdhc2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc2_2>;

	pinctrl-0 = <&pinctrl_usdhc2>;

	cd-gpios = <&gpio1 4 0>;

	wp-gpios = <&gpio1 2 0>;

	status = "disabled";
@@ -172,8 +235,8 @@ 


&usdhc3 {

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_usdhc3_2

		     &pinctrl_usdhc3_pfla02>;

        pinctrl-0 = <&pinctrl_usdhc3

		     &pinctrl_usdhc3_cdwp>;

        cd-gpios = <&gpio1 27 0>;

        wp-gpios = <&gpio1 29 0>;

        status = "disabled";

arch/arm/boot/dts/imx6q-sabrelite.dts

+89 −9
Original line number Diff line number Diff line
@@ -68,14 +68,14 @@ 
&audmux {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_audmux_1>;

	pinctrl-0 = <&pinctrl_audmux>;

};



&ecspi1 {

	fsl,spi-num-chipselects = <1>;

	cs-gpios = <&gpio3 19 0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi1_1>;

	pinctrl-0 = <&pinctrl_ecspi1>;

	status = "okay";



	flash: m25p80@0 {
@@ -87,7 +87,7 @@ 


&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet_1>;

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	phy-reset-gpios = <&gpio3 23 0>;

	status = "okay";
@@ -97,7 +97,7 @@ 
	status = "okay";

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1_1>;

	pinctrl-0 = <&pinctrl_i2c1>;



	codec: sgtl5000@0a {

		compatible = "fsl,sgtl5000";
@@ -112,7 +112,7 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;



	hog {

	imx6q-sabrelite {

		pinctrl_hog: hoggrp {

			fsl,pins = <

				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
@@ -126,6 +126,86 @@ 
				MX6QDL_PAD_EIM_D23__GPIO3_IO23	0x80000000

			>;

		};



		pinctrl_audmux: audmuxgrp {

			fsl,pins = <

				MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x80000000

				MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x80000000

				MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x80000000

				MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x80000000

			>;

		};



		pinctrl_ecspi1: ecspi1grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1

				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1

				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1

			>;

		};



		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8

			>;

		};



		pinctrl_i2c1: i2c1grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1

				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1

			>;

		};



		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usbotg: usbotggrp {

			fsl,pins = <

				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};



		pinctrl_usdhc4: usdhc4grp {

			fsl,pins = <

				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059

				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059

				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059

				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059

				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059

				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059

			>;

		};

	};

};
@@ -166,7 +246,7 @@ 
&uart2 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2_1>;

	pinctrl-0 = <&pinctrl_uart2>;

};



&usbh1 {
@@ -176,14 +256,14 @@ 
&usbotg {

	vbus-supply = <&reg_usb_otg_vbus>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbotg_1>;

	pinctrl-0 = <&pinctrl_usbotg>;

	disable-over-current;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3_2>;

	pinctrl-0 = <&pinctrl_usdhc3>;

	cd-gpios = <&gpio7 0 0>;

	wp-gpios = <&gpio7 1 0>;

	vmmc-supply = <&reg_3p3v>;
@@ -192,7 +272,7 @@ 


&usdhc4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc4_2>;

	pinctrl-0 = <&pinctrl_usdhc4>;

	cd-gpios = <&gpio2 6 0>;

	wp-gpios = <&gpio2 7 0>;

	vmmc-supply = <&reg_3p3v>;

arch/arm/boot/dts/imx6q-sbc6x.dts

+54 −4
Original line number Diff line number Diff line
@@ -17,28 +17,78 @@ 
	};

};





&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet_1>;

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	status = "okay";

};



&iomuxc {

	imx6q-sbc6x {

		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8

			>;

		};



		pinctrl_uart1: uart1grp {

			fsl,pins = <

				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1

				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usbotg: usbotggrp {

			fsl,pins = <

				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};

	};

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1_1>;

	pinctrl-0 = <&pinctrl_uart1>;

	status = "okay";

};



&usbotg {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbotg_1>;

	pinctrl-0 = <&pinctrl_usbotg>;

	disable-over-current;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3_2>;

	pinctrl-0 = <&pinctrl_usdhc3>;

	status = "okay";

};

arch/arm/boot/dts/imx6q-udoo.dts

+24 −2
Original line number Diff line number Diff line
@@ -21,19 +21,41 @@ 
	};

};



&iomuxc {

	imx6q-udoo {

		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};

	};

};



&sata {

	status = "okay";

};



&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2_1>;

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3_2>;

	pinctrl-0 = <&pinctrl_usdhc3>;

	non-removable;

	status = "okay";

};