Merge remote-tracking branches 'spi/topic/s3c64xx', 'spi/topic/sc18is602',...

Renesas HSPI.

Required properties:

- compatible : 	"renesas,hspi"

- compatible       : "renesas,hspi-<soctype>", "renesas,hspi" as fallback.

		     Examples with soctypes are:

		       - "renesas,hspi-r8a7778" (R-Car M1)

		       - "renesas,hspi-r8a7779" (R-Car H1)

- reg              : Offset and length of the register set for the device

- interrupts : interrupt line used by HSPI

- interrupt-parent : The phandle for the interrupt controller that

		     services interrupts for this device

- interrupts       : Interrupt specifier

- #address-cells   : Must be <1>

- #size-cells      : Must be <0>

Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.

Example:

	hspi0: spi@fffc7000 {

		compatible = "renesas,hspi-r8a7778", "renesas,hspi";

		reg = <0xfffc7000 0x18>;

		interrupt-parent = <&gic>;

		interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};

Renesas MSIOF spi controller

Required properties:

- compatible : 	"renesas,sh-msiof" for SuperH or

		"renesas,sh-mobile-msiof" for SH Mobile series

- compatible           : "renesas,msiof-<soctype>" for SoCs,

			 "renesas,sh-msiof" for SuperH, or

			 "renesas,sh-mobile-msiof" for SH Mobile series.

			 Examples with soctypes are:

			 "renesas,msiof-r8a7790" (R-Car H2)

			 "renesas,msiof-r8a7791" (R-Car M2)

- reg                  : Offset and length of the register set for the device

- interrupts : interrupt line used by MSIOF

- interrupt-parent     : The phandle for the interrupt controller that

			 services interrupts for this device

- interrupts           : Interrupt specifier

- #address-cells       : Must be <1>

- #size-cells          : Must be <0>

Optional properties:

- num-cs		: total number of chip-selects

- clocks               : Must contain a reference to the functional clock.

- num-cs               : Total number of chip-selects (default is 1)

Optional properties, deprecated for soctype-specific bindings:

- renesas,tx-fifo-size : Overrides the default tx fifo size given in words

			 (default is 64)

- renesas,rx-fifo-size : Overrides the default rx fifo size given in words

			 (default is 64, or 256 on R-Car H2 and M2)

Pinctrl properties might be needed, too.  See

Documentation/devicetree/bindings/pinctrl/renesas,*.

Example:

	msiof0: spi@e6e20000 {

		compatible = "renesas,msiof-r8a7791";

		reg = <0 0xe6e20000 0 0x0064>;

		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};

	SPI_MODE_0..SPI_MODE_3; or if you prefer you can combine SPI_CPOL

	(clock polarity, idle high iff this is set) or SPI_CPHA (clock phase,

	sample on trailing edge iff this is set) flags.

	Note that this request is limited to SPI mode flags that fit in a

	single byte.

    SPI_IOC_RD_MODE32, SPI_IOC_WR_MODE32 ... pass a pointer to a uin32_t

	which will return (RD) or assign (WR) the full SPI transfer mode,

	not limited to the bits that fit in one byte.

    SPI_IOC_RD_LSB_FIRST, SPI_IOC_WR_LSB_FIRST ... pass a pointer to a byte

	which will return (RD) or assign (WR) the bit justification used to

static void dumpstat(const char *name, int fd)

{

	__u8	mode, lsb, bits;

	__u32	speed;

	__u8	lsb, bits;

	__u32	mode, speed;

	if (ioctl(fd, SPI_IOC_RD_MODE, &mode) < 0) {

	if (ioctl(fd, SPI_IOC_RD_MODE32, &mode) < 0) {

		perror("SPI rd_mode");

		return;

	}

		return;

	}

	printf("%s: spi mode %d, %d bits %sper word, %d Hz max\n",

	printf("%s: spi mode 0x%x, %d bits %sper word, %d Hz max\n",

		name, mode, bits, lsb ? "(lsb first) " : "", speed);

}

}

static const char *device = "/dev/spidev1.1";

static uint8_t mode;

static uint32_t mode;

static uint8_t bits = 8;

static uint32_t speed = 500000;

static uint16_t delay;

		.bits_per_word = bits,

	};

	if (mode & SPI_TX_QUAD)

		tr.tx_nbits = 4;

	else if (mode & SPI_TX_DUAL)

		tr.tx_nbits = 2;

	if (mode & SPI_RX_QUAD)

		tr.rx_nbits = 4;

	else if (mode & SPI_RX_DUAL)

		tr.rx_nbits = 2;

	if (!(mode & SPI_LOOP)) {

		if (mode & (SPI_TX_QUAD | SPI_TX_DUAL))

			tr.rx_buf = 0;

		else if (mode & (SPI_RX_QUAD | SPI_RX_DUAL))

			tr.tx_buf = 0;

	}

	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);

	if (ret < 1)

		pabort("can't send spi message");

	     "  -O --cpol     clock polarity\n"

	     "  -L --lsb      least significant bit first\n"

	     "  -C --cs-high  chip select active high\n"

	     "  -3 --3wire    SI/SO signals shared\n");

	     "  -3 --3wire    SI/SO signals shared\n"

	     "  -N --no-cs    no chip select\n"

	     "  -R --ready    slave pulls low to pause\n"

	     "  -2 --dual     dual transfer\n"

	     "  -4 --quad     quad transfer\n");

	exit(1);

}

			{ "3wire",   0, 0, '3' },

			{ "no-cs",   0, 0, 'N' },

			{ "ready",   0, 0, 'R' },

			{ "dual",    0, 0, '2' },

			{ "quad",    0, 0, '4' },

			{ NULL, 0, 0, 0 },

		};

		int c;

		c = getopt_long(argc, argv, "D:s:d:b:lHOLC3NR", lopts, NULL);

		c = getopt_long(argc, argv, "D:s:d:b:lHOLC3NR24", lopts, NULL);

		if (c == -1)

			break;

		case 'R':

			mode |= SPI_READY;

			break;

		case '2':

			mode |= SPI_TX_DUAL;

			break;

		case '4':

			mode |= SPI_TX_QUAD;

			break;

		default:

			print_usage(argv[0]);

			break;

		}

	}

	if (mode & SPI_LOOP) {

		if (mode & SPI_TX_DUAL)

			mode |= SPI_RX_DUAL;

		if (mode & SPI_TX_QUAD)

			mode |= SPI_RX_QUAD;

	}

}

int main(int argc, char *argv[])

	/*

	 * spi mode

	 */

	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);

	ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);

	if (ret == -1)

		pabort("can't set spi mode");

	ret = ioctl(fd, SPI_IOC_RD_MODE, &mode);

	ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);

	if (ret == -1)

		pabort("can't get spi mode");

	if (ret == -1)

		pabort("can't get max speed hz");

	printf("spi mode: %d\n", mode);

	printf("spi mode: 0x%x\n", mode);

	printf("bits per word: %d\n", bits);

	printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);