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Commit 810f1512 authored by James Cosin's avatar James Cosin Committed by Bob Liu
Browse files

Blackfin: cpufreq: fix dpm_state_table 



This patch fixes an assumption that cclk's initial divisor will always be 1 (or
0 in the register).  TSCALE is always initialized on startup with a value of 4
regardless of the inital cclk divisor; so, we can't make the assumption without
making lots of other assumptions.  The TPERIOD value is set with a value of the
current cclk (value / (HZ * TSCALE)) - 1; so, we need to adjust based on this
initial frequency and not use cclk's initial divisor for adjusting the tscale.

Signed-off-by: default avatarSteven Miao <realmz6@gmail.com>
Signed-off-by: default avatarBob Liu <lliubbo@gmail.com>
parent ce860914

arch/blackfin/mach-common/cpufreq.c

+2 −3
Original line number Diff line number Diff line
@@ -77,15 +77,14 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) 
	csel = bfin_read32(CGU0_DIV) & 0x1F;

#endif



	for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {

	for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {

		bfin_freq_table[index].frequency = cclk >> index;

#ifndef CONFIG_BF60x

		dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */

		dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;

#else

		dpm_state_table[index].csel = csel;

		dpm_state_table[index].tscale =  TIME_SCALE >> index;

#endif

		dpm_state_table[index].tscale =  (TIME_SCALE >> index) - 1;



		pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",

						 bfin_freq_table[index].frequency,