sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support (80da8e02) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/pinctrl/sh-pfc/pfc-r8a7740.c

+220 −145

Original line number	Original line	Diff line number	Diff line
	@@ -18,10 +18,14 @@
	* along with this program; if not, write to the Free Software		* along with this program; if not, write to the Free Software
	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA		* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	*/		*/
			#include <linux/io.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>
			#include <linux/pinctrl/pinconf-generic.h>

	#include <mach/r8a7740.h>		#include <mach/r8a7740.h>
	#include <mach/irqs.h>		#include <mach/irqs.h>

			#include "core.h"
	#include "sh_pfc.h"		#include "sh_pfc.h"

	#define CPU_ALL_PORT(fn, pfx, sfx) \		#define CPU_ALL_PORT(fn, pfx, sfx) \
	@@ -66,16 +70,6 @@ enum {
	PORT_ALL(IN),		PORT_ALL(IN),
	PINMUX_INPUT_END,		PINMUX_INPUT_END,

	/* PORT0_IN_PU -> PORT211_IN_PU */
	PINMUX_INPUT_PULLUP_BEGIN,
	PORT_ALL(IN_PU),
	PINMUX_INPUT_PULLUP_END,

	/* PORT0_IN_PD -> PORT211_IN_PD */
	PINMUX_INPUT_PULLDOWN_BEGIN,
	PORT_ALL(IN_PD),
	PINMUX_INPUT_PULLDOWN_END,

	/* PORT0_OUT -> PORT211_OUT */		/* PORT0_OUT -> PORT211_OUT */
	PINMUX_OUTPUT_BEGIN,		PINMUX_OUTPUT_BEGIN,
	PORT_ALL(OUT),		PORT_ALL(OUT),
	@@ -596,137 +590,11 @@ enum {
	PINMUX_MARK_END,		PINMUX_MARK_END,
	};		};

			#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
			#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)

	static const pinmux_enum_t pinmux_data[] = {		static const pinmux_enum_t pinmux_data[] = {
	/* specify valid pin states for each pin in GPIO mode */		PINMUX_DATA_GP_ALL(),

	/* I/O and Pull U/D */
	PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
	PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
	PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
	PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
	PORT_DATA_IO(8), PORT_DATA_IO(9),

	PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
	PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
	PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
	PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
	PORT_DATA_IO(18), PORT_DATA_IO_PU(19),

	PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
	PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
	PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
	PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
	PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),

	PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
	PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
	PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
	PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
	PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),

	PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
	PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
	PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
	PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
	PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),

	PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
	PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
	PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
	PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
	PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),

	PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
	PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
	PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
	PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
	PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),

	PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
	PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
	PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
	PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
	PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),

	PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
	PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
	PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
	PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
	PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),

	PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
	PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
	PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
	PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
	PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),

	PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
	PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
	PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
	PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
	PORT_DATA_IO(108), PORT_DATA_IO(109),

	PORT_DATA_IO(110), PORT_DATA_IO(111),
	PORT_DATA_IO(112), PORT_DATA_IO(113),
	PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
	PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
	PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),

	PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
	PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
	PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
	PORT_DATA_IO(126), PORT_DATA_IO(127),
	PORT_DATA_IO(128), PORT_DATA_IO(129),

	PORT_DATA_IO(130), PORT_DATA_IO(131),
	PORT_DATA_IO(132), PORT_DATA_IO(133),
	PORT_DATA_IO(134), PORT_DATA_IO(135),
	PORT_DATA_IO(136), PORT_DATA_IO(137),
	PORT_DATA_IO(138), PORT_DATA_IO(139),

	PORT_DATA_IO(140), PORT_DATA_IO(141),
	PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
	PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
	PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
	PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),

	PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
	PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
	PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
	PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
	PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),

	PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
	PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
	PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
	PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
	PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),

	PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
	PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
	PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
	PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
	PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),

	PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
	PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
	PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
	PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
	PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),

	PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
	PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
	PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
	PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
	PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),

	PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
	PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
	PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
	PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
	PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),

	PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),

	/* Port0 */		/* Port0 */
	PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),		PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
	@@ -1669,8 +1537,138 @@ static const pinmux_enum_t pinmux_data[] = {
	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),		PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
	};		};

			#define R8A7740_PIN(pin, cfgs) \
			{ \
			.name = __stringify(PORT##pin), \
			.enum_id = PORT##pin##_DATA, \
			.configs = cfgs, \
			}

			#define __I (SH_PFC_PIN_CFG_INPUT)
			#define __O (SH_PFC_PIN_CFG_OUTPUT)
			#define __IO (SH_PFC_PIN_CFG_INPUT \| SH_PFC_PIN_CFG_OUTPUT)
			#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
			#define __PU (SH_PFC_PIN_CFG_PULL_UP)
			#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN \| SH_PFC_PIN_CFG_PULL_UP)

			#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I \| __PD)
			#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I \| __PU)
			#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I \| __PUD)
			#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
			#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO \| __PD)
			#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO \| __PU)
			#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO \| __PUD)
			#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
			#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O \| __PUD)

	static struct sh_pfc_pin pinmux_pins[] = {		static struct sh_pfc_pin pinmux_pins[] = {
	GPIO_PORT_ALL(),		/* Table 56-1 (I/O and Pull U/D) */
			R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
			R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
			R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
			R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
			R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
			R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
			R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
			R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
			R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
			R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
			R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
			R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
			R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
			R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
			R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
			R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
			R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
			R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
			R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
			R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
			R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
			R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
			R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
			R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
			R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
			R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
			R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
			R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
			R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
			R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
			R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
			R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
			R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
			R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
			R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
			R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
			R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
			R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
			R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
			R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
			R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
			R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
			R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
			R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
			R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
			R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
			R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
			R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
			R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
			R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
			R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
			R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
			R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
			R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
			R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
			R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
			R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
			R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
			R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
			R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
			R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
			R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
			R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
			R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
			R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
			R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
			R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
			R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
			R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
			R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
			R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
			R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
			R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
			R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
			R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
			R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
			R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
			R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
			R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
			R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
			R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
			R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
			R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
			R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
			R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
			R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
			R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
			R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
			R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
			R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
			R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
			R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
			R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
			R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
			R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
			R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
			R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
			R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
			R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
			R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
			R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
			R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
			R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
			R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
			R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
			R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
	};		};

	/* - BSC -------------------------------------------------------------------- */		/* - BSC -------------------------------------------------------------------- */
	@@ -3204,6 +3202,17 @@ static const struct sh_pfc_function pinmux_functions[] = {
	SH_PFC_FUNCTION(sdhi2),		SH_PFC_FUNCTION(sdhi2),
	};		};

			#undef PORTCR
			#define PORTCR(nr, reg) \
			{ \
			PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
			_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
			PORT##nr##_FN0, PORT##nr##_FN1, \
			PORT##nr##_FN2, PORT##nr##_FN3, \
			PORT##nr##_FN4, PORT##nr##_FN5, \
			PORT##nr##_FN6, PORT##nr##_FN7 } \
			}

	static const struct pinmux_cfg_reg pinmux_config_regs[] = {		static const struct pinmux_cfg_reg pinmux_config_regs[] = {
	PORTCR(0, 0xe6050000), /* PORT0CR */		PORTCR(0, 0xe6050000), /* PORT0CR */
	PORTCR(1, 0xe6050001), /* PORT1CR */		PORTCR(1, 0xe6050001), /* PORT1CR */
	@@ -3657,14 +3666,80 @@ static const struct pinmux_irq pinmux_irqs[] = {
	PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */		PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
	};		};

			#define PORTnCR_PULMD_OFF (0 << 6)
			#define PORTnCR_PULMD_DOWN (2 << 6)
			#define PORTnCR_PULMD_UP (3 << 6)
			#define PORTnCR_PULMD_MASK (3 << 6)

			struct r8a7740_portcr_group {
			unsigned int end_pin;
			unsigned int offset;
			};

			static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
			{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
			};

			static void __iomem r8a7740_pinmux_portcr(struct sh_pfc pfc, unsigned int pin)
			{
			unsigned int i;

			for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
			const struct r8a7740_portcr_group *group =
			&r8a7740_portcr_offsets[i];

			if (i <= group->end_pin)
			return pfc->window->virt + group->offset + pin;
			}

			return NULL;
			}

			static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
			{
			void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
			u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;

			switch (value) {
			case PORTnCR_PULMD_UP:
			return PIN_CONFIG_BIAS_PULL_UP;
			case PORTnCR_PULMD_DOWN:
			return PIN_CONFIG_BIAS_PULL_DOWN;
			case PORTnCR_PULMD_OFF:
			default:
			return PIN_CONFIG_BIAS_DISABLE;
			}
			}

			static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
			unsigned int bias)
			{
			void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
			u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;

			switch (bias) {
			case PIN_CONFIG_BIAS_PULL_UP:
			value \|= PORTnCR_PULMD_UP;
			break;
			case PIN_CONFIG_BIAS_PULL_DOWN:
			value \|= PORTnCR_PULMD_DOWN;
			break;
			}

			iowrite8(value, addr);
			}

			static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
			.get_bias = r8a7740_pinmux_get_bias,
			.set_bias = r8a7740_pinmux_set_bias,
			};

	const struct sh_pfc_soc_info r8a7740_pinmux_info = {		const struct sh_pfc_soc_info r8a7740_pinmux_info = {
	.name = "r8a7740_pfc",		.name = "r8a7740_pfc",
			.ops = &r8a7740_pinmux_ops,

	.input = { PINMUX_INPUT_BEGIN,		.input = { PINMUX_INPUT_BEGIN,
	PINMUX_INPUT_END },		PINMUX_INPUT_END },
	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
	PINMUX_INPUT_PULLUP_END },
	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
	PINMUX_INPUT_PULLDOWN_END },
	.output = { PINMUX_OUTPUT_BEGIN,		.output = { PINMUX_OUTPUT_BEGIN,
	PINMUX_OUTPUT_END },		PINMUX_OUTPUT_END },
	.function = { PINMUX_FUNCTION_BEGIN,		.function = { PINMUX_FUNCTION_BEGIN,