Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +29 −21 Original line number Diff line number Diff line Loading @@ -889,7 +889,6 @@ static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl, if (packet->payload_length > 0) buf[3] |= BIT(6); buf[3] |= BIT(7); /* send embedded BTA for read commands */ if ((buf[2] & 0x3f) == MIPI_DSI_DCS_READ) Loading Loading @@ -953,20 +952,21 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, goto error; } if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl, &packet, &buffer, &length); if (rc) { pr_err("[%s] failed to copy message, rc=%d\n", dsi_ctrl->name, rc); goto error; } if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) buffer[3] |= BIT(7);//set the last cmd bit in header. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { cmd_mem.offset = dsi_ctrl->cmd_buffer_iova; cmd_mem.length = length; cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? true : false; cmd_mem.is_master = (flags & DSI_CTRL_CMD_BROADCAST_MASTER) ? Loading @@ -975,19 +975,20 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, true : false; cmdbuf = (u8 *)(dsi_ctrl->vaddr); for (cnt = 0; cnt < length; cnt++) cmdbuf[cnt] = buffer[cnt]; cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt]; } else if (flags & DSI_CTRL_CMD_FIFO_STORE) { rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl, &packet, &buffer, &length); if (rc) { pr_err("[%s] failed to copy message, rc=%d\n", dsi_ctrl->name, rc); dsi_ctrl->cmd_len += length; if (!(msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) { goto error; } else { cmd_mem.length = dsi_ctrl->cmd_len; dsi_ctrl->cmd_len = 0; } } else if (flags & DSI_CTRL_CMD_FIFO_STORE) { cmd.command = (u32 *)buffer; cmd.size = length; cmd.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? Loading @@ -1001,6 +1002,9 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ? DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0; if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) hw_flags |= DSI_CTRL_CMD_LAST_COMMAND; if (flags & DSI_CTRL_CMD_DEFER_TRIGGER) { if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { dsi_ctrl->hw.ops.kickoff_command(&dsi_ctrl->hw, Loading Loading @@ -2487,6 +2491,10 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) return -EINVAL; } /* Dont trigger the command if this is not the last ocmmand */ if (!(flags & DSI_CTRL_CMD_LAST_COMMAND)) return rc; mutex_lock(&dsi_ctrl->ctrl_lock); if (!(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +4 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,8 @@ * reading data from memory. * @DSI_CTRL_CMD_FETCH_MEMORY: Fetch command from memory through AXI bus * and transfer it. * @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last * command in the batch. */ #define DSI_CTRL_CMD_READ 0x1 #define DSI_CTRL_CMD_BROADCAST 0x2 Loading @@ -42,6 +44,7 @@ #define DSI_CTRL_CMD_DEFER_TRIGGER 0x8 #define DSI_CTRL_CMD_FIFO_STORE 0x10 #define DSI_CTRL_CMD_FETCH_MEMORY 0x20 #define DSI_CTRL_CMD_LAST_COMMAND 0x40 /** * enum dsi_power_state - defines power states for dsi controller. Loading Loading @@ -225,6 +228,7 @@ struct dsi_ctrl { struct drm_gem_object *tx_cmd_buf; u32 cmd_buffer_size; u32 cmd_buffer_iova; u32 cmd_len; void *vaddr; /* Debug Information */ Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +4 −0 Original line number Diff line number Diff line Loading @@ -1707,6 +1707,10 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY); if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) { flags |= DSI_CTRL_CMD_LAST_COMMAND; m_flags |= DSI_CTRL_CMD_LAST_COMMAND; } /* * 1. Setup commands in FIFO * 2. Trigger commands Loading drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -497,6 +497,9 @@ static int dsi_panel_tx_cmd_set(struct dsi_panel *panel, if (state == DSI_CMD_SET_STATE_LP) cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; if (cmds->last_command) cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; len = ops->transfer(panel->host, &cmds->msg); if (len < 0) { rc = len; Loading include/drm/drm_mipi_dsi.h +2 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ struct mipi_dsi_device; #define MIPI_DSI_MSG_USE_LPM BIT(1) /* read mipi_dsi_msg.ctrl and unicast to only that ctrls */ #define MIPI_DSI_MSG_UNICAST BIT(2) /* Stack all commands until lastcommand bit and trigger all in one go */ #define MIPI_DSI_MSG_LASTCOMMAND BIT(3) /** * struct mipi_dsi_msg - read/write DSI buffer Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +29 −21 Original line number Diff line number Diff line Loading @@ -889,7 +889,6 @@ static int dsi_ctrl_copy_and_pad_cmd(struct dsi_ctrl *dsi_ctrl, if (packet->payload_length > 0) buf[3] |= BIT(6); buf[3] |= BIT(7); /* send embedded BTA for read commands */ if ((buf[2] & 0x3f) == MIPI_DSI_DCS_READ) Loading Loading @@ -953,20 +952,21 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, goto error; } if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl, &packet, &buffer, &length); if (rc) { pr_err("[%s] failed to copy message, rc=%d\n", dsi_ctrl->name, rc); goto error; } if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) buffer[3] |= BIT(7);//set the last cmd bit in header. if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { cmd_mem.offset = dsi_ctrl->cmd_buffer_iova; cmd_mem.length = length; cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? true : false; cmd_mem.is_master = (flags & DSI_CTRL_CMD_BROADCAST_MASTER) ? Loading @@ -975,19 +975,20 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, true : false; cmdbuf = (u8 *)(dsi_ctrl->vaddr); for (cnt = 0; cnt < length; cnt++) cmdbuf[cnt] = buffer[cnt]; cmdbuf[dsi_ctrl->cmd_len + cnt] = buffer[cnt]; } else if (flags & DSI_CTRL_CMD_FIFO_STORE) { rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl, &packet, &buffer, &length); if (rc) { pr_err("[%s] failed to copy message, rc=%d\n", dsi_ctrl->name, rc); dsi_ctrl->cmd_len += length; if (!(msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) { goto error; } else { cmd_mem.length = dsi_ctrl->cmd_len; dsi_ctrl->cmd_len = 0; } } else if (flags & DSI_CTRL_CMD_FIFO_STORE) { cmd.command = (u32 *)buffer; cmd.size = length; cmd.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ? Loading @@ -1001,6 +1002,9 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, hw_flags |= (flags & DSI_CTRL_CMD_DEFER_TRIGGER) ? DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER : 0; if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) hw_flags |= DSI_CTRL_CMD_LAST_COMMAND; if (flags & DSI_CTRL_CMD_DEFER_TRIGGER) { if (flags & DSI_CTRL_CMD_FETCH_MEMORY) { dsi_ctrl->hw.ops.kickoff_command(&dsi_ctrl->hw, Loading Loading @@ -2487,6 +2491,10 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) return -EINVAL; } /* Dont trigger the command if this is not the last ocmmand */ if (!(flags & DSI_CTRL_CMD_LAST_COMMAND)) return rc; mutex_lock(&dsi_ctrl->ctrl_lock); if (!(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +4 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,8 @@ * reading data from memory. * @DSI_CTRL_CMD_FETCH_MEMORY: Fetch command from memory through AXI bus * and transfer it. * @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last * command in the batch. */ #define DSI_CTRL_CMD_READ 0x1 #define DSI_CTRL_CMD_BROADCAST 0x2 Loading @@ -42,6 +44,7 @@ #define DSI_CTRL_CMD_DEFER_TRIGGER 0x8 #define DSI_CTRL_CMD_FIFO_STORE 0x10 #define DSI_CTRL_CMD_FETCH_MEMORY 0x20 #define DSI_CTRL_CMD_LAST_COMMAND 0x40 /** * enum dsi_power_state - defines power states for dsi controller. Loading Loading @@ -225,6 +228,7 @@ struct dsi_ctrl { struct drm_gem_object *tx_cmd_buf; u32 cmd_buffer_size; u32 cmd_buffer_iova; u32 cmd_len; void *vaddr; /* Debug Information */ Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +4 −0 Original line number Diff line number Diff line Loading @@ -1707,6 +1707,10 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY); if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) { flags |= DSI_CTRL_CMD_LAST_COMMAND; m_flags |= DSI_CTRL_CMD_LAST_COMMAND; } /* * 1. Setup commands in FIFO * 2. Trigger commands Loading
drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -497,6 +497,9 @@ static int dsi_panel_tx_cmd_set(struct dsi_panel *panel, if (state == DSI_CMD_SET_STATE_LP) cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; if (cmds->last_command) cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; len = ops->transfer(panel->host, &cmds->msg); if (len < 0) { rc = len; Loading
include/drm/drm_mipi_dsi.h +2 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ struct mipi_dsi_device; #define MIPI_DSI_MSG_USE_LPM BIT(1) /* read mipi_dsi_msg.ctrl and unicast to only that ctrls */ #define MIPI_DSI_MSG_UNICAST BIT(2) /* Stack all commands until lastcommand bit and trigger all in one go */ #define MIPI_DSI_MSG_LASTCOMMAND BIT(3) /** * struct mipi_dsi_msg - read/write DSI buffer Loading