Loading Documentation/devicetree/bindings/arm/arch_timer.txt +6 −0 Original line number Diff line number Diff line Loading @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. - hisilicon,erratum-161010101 : A boolean property. Indicates the presence of Hisilicon erratum 161010101, which says that reading the counters is unreliable in some cases, and reads may return a value 32 beyond the correct value. This also affects writes to the tval registers, due to the implicit counter read. ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 60 SUBLEVEL = 61 EXTRAVERSION = NAME = Roaring Lionus Loading arch/arm/boot/dts/armada-375.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -176,9 +176,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading arch/arm/boot/dts/armada-38x.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -143,9 +143,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading arch/arm/boot/dts/armada-39x.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -111,9 +111,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading Loading
Documentation/devicetree/bindings/arm/arch_timer.txt +6 −0 Original line number Diff line number Diff line Loading @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. - hisilicon,erratum-161010101 : A boolean property. Indicates the presence of Hisilicon erratum 161010101, which says that reading the counters is unreliable in some cases, and reads may return a value 32 beyond the correct value. This also affects writes to the tval registers, due to the implicit counter read. ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 60 SUBLEVEL = 61 EXTRAVERSION = NAME = Roaring Lionus Loading
arch/arm/boot/dts/armada-375.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -176,9 +176,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading
arch/arm/boot/dts/armada-38x.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -143,9 +143,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading
arch/arm/boot/dts/armada-39x.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -111,9 +111,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; arm,double-linefill = <1>; arm,double-linefill = <0>; prefetch-data = <1>; }; Loading