Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +22 −3 Original line number Diff line number Diff line Loading @@ -970,9 +970,18 @@ static int cam_vfe_bus_acquire_wm( rsrc_data->en_cfg = 0x1; } else { /* Write master 5-6 DS ports, 10 PDAF */ uint32_t align_width; rsrc_data->width = rsrc_data->width * 4; rsrc_data->height = rsrc_data->height / 2; rsrc_data->en_cfg = 0x1; CAM_DBG(CAM_ISP, "before width %d", rsrc_data->width); align_width = ALIGNUP(rsrc_data->width, 16); if (align_width != rsrc_data->width) { CAM_WARN(CAM_ISP, "Override width %u with expected %u", rsrc_data->width, align_width); rsrc_data->width = align_width; } } *client_done_mask = (1 << wm_idx); Loading Loading @@ -2268,7 +2277,7 @@ static int cam_vfe_bus_update_buf(void *priv, void *cmd_args, struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; uint32_t *reg_val_pair; uint32_t i, j, size = 0; uint32_t frame_inc = 0; uint32_t frame_inc = 0, val; bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; update_buf = (struct cam_isp_hw_get_buf_update *) cmd_args; Loading Loading @@ -2309,12 +2318,22 @@ static int cam_vfe_bus_update_buf(void *priv, void *cmd_args, wm_data->index, wm_data->width); /* For initial configuration program all bus registers */ if ((wm_data->stride != io_cfg->planes[i].plane_stride || val = io_cfg->planes[i].plane_stride; CAM_DBG(CAM_ISP, "before stride %d", val); val = ALIGNUP(val, 16); if (val != io_cfg->planes[i].plane_stride && val != wm_data->stride) CAM_WARN(CAM_ISP, "Warning stride %u expected %u", io_cfg->planes[i].plane_stride, val); if ((wm_data->stride != val || !wm_data->init_cfg_done) && (wm_data->index >= 3)) { CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->stride, io_cfg->planes[i].plane_stride); wm_data->stride = io_cfg->planes[i].plane_stride; wm_data->stride = val; CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", wm_data->index, wm_data->stride); } Loading Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +22 −3 Original line number Diff line number Diff line Loading @@ -970,9 +970,18 @@ static int cam_vfe_bus_acquire_wm( rsrc_data->en_cfg = 0x1; } else { /* Write master 5-6 DS ports, 10 PDAF */ uint32_t align_width; rsrc_data->width = rsrc_data->width * 4; rsrc_data->height = rsrc_data->height / 2; rsrc_data->en_cfg = 0x1; CAM_DBG(CAM_ISP, "before width %d", rsrc_data->width); align_width = ALIGNUP(rsrc_data->width, 16); if (align_width != rsrc_data->width) { CAM_WARN(CAM_ISP, "Override width %u with expected %u", rsrc_data->width, align_width); rsrc_data->width = align_width; } } *client_done_mask = (1 << wm_idx); Loading Loading @@ -2268,7 +2277,7 @@ static int cam_vfe_bus_update_buf(void *priv, void *cmd_args, struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; uint32_t *reg_val_pair; uint32_t i, j, size = 0; uint32_t frame_inc = 0; uint32_t frame_inc = 0, val; bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; update_buf = (struct cam_isp_hw_get_buf_update *) cmd_args; Loading Loading @@ -2309,12 +2318,22 @@ static int cam_vfe_bus_update_buf(void *priv, void *cmd_args, wm_data->index, wm_data->width); /* For initial configuration program all bus registers */ if ((wm_data->stride != io_cfg->planes[i].plane_stride || val = io_cfg->planes[i].plane_stride; CAM_DBG(CAM_ISP, "before stride %d", val); val = ALIGNUP(val, 16); if (val != io_cfg->planes[i].plane_stride && val != wm_data->stride) CAM_WARN(CAM_ISP, "Warning stride %u expected %u", io_cfg->planes[i].plane_stride, val); if ((wm_data->stride != val || !wm_data->init_cfg_done) && (wm_data->index >= 3)) { CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->stride, io_cfg->planes[i].plane_stride); wm_data->stride = io_cfg->planes[i].plane_stride; wm_data->stride = val; CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", wm_data->index, wm_data->stride); } Loading