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Commit 7f813377 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add tiling support to the cs checker for r6xx/r7xx 



Check for relocs for DB_DEPTH_INFO, CB_COLOR*_INFO, and texture
resources.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 97d66328

drivers/gpu/drm/radeon/r600_cs.c

+51 −6
Original line number Diff line number Diff line
@@ -725,6 +725,24 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx 
		track->db_depth_control = radeon_get_ib_value(p, idx);

		break;

	case R_028010_DB_DEPTH_INFO:

		if (r600_cs_packet_next_is_pkt3_nop(p)) {

			r = r600_cs_packet_next_reloc(p, &reloc);

			if (r) {

				dev_warn(p->dev, "bad SET_CONTEXT_REG "

					 "0x%04X\n", reg);

				return -EINVAL;

			}

			track->db_depth_info = radeon_get_ib_value(p, idx);

			ib[idx] &= C_028010_ARRAY_MODE;

			track->db_depth_info &= C_028010_ARRAY_MODE;

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

				ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);

				track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);

			} else {

				ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);

				track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);

			}

		} else

			track->db_depth_info = radeon_get_ib_value(p, idx);

		break;

	case R_028004_DB_DEPTH_VIEW:
@@ -758,8 +776,25 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx 
	case R_0280B4_CB_COLOR5_INFO:

	case R_0280B8_CB_COLOR6_INFO:

	case R_0280BC_CB_COLOR7_INFO:

		if (r600_cs_packet_next_is_pkt3_nop(p)) {

			r = r600_cs_packet_next_reloc(p, &reloc);

			if (r) {

				dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);

				return -EINVAL;

			}

			tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;

			track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {

				ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);

				track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);

			} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {

				ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);

				track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);

			}

		} else {

			tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;

			track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

		}

		break;

	case R_028060_CB_COLOR0_SIZE:

	case R_028064_CB_COLOR1_SIZE:
@@ -987,7 +1022,8 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels 
 */

static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,

					      struct radeon_bo *texture,

						struct radeon_bo *mipmap)

					      struct radeon_bo *mipmap,

					      u32 tiling_flags)

{

	u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;

	u32 word0, word1, l0_size, mipmap_size;
@@ -995,7 +1031,12 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i 
	/* on legacy kernel we don't perform advanced check */

	if (p->rdev == NULL)

		return 0;



	word0 = radeon_get_ib_value(p, idx + 0);

	if (tiling_flags & RADEON_TILING_MACRO)

		word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);

	else if (tiling_flags & RADEON_TILING_MICRO)

		word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);

	word1 = radeon_get_ib_value(p, idx + 1);

	w0 = G_038000_TEX_WIDTH(word0) + 1;

	h0 = G_038004_TEX_HEIGHT(word1) + 1;
@@ -1240,6 +1281,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
					return -EINVAL;

				}

				ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

					ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);

				else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)

					ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);

				texture = reloc->robj;

				/* tex mip base */

				r = r600_cs_packet_next_reloc(p, &reloc);
@@ -1250,7 +1295,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
				ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				mipmap = reloc->robj;

				r = r600_check_texture_resource(p,  idx+(i*7)+1,

						texture, mipmap);

								texture, mipmap, reloc->lobj.tiling_flags);

				if (r)

					return r;

				break;

drivers/gpu/drm/radeon/r600d.h

+6 −0
Original line number Diff line number Diff line
@@ -1159,6 +1159,10 @@ 
#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)

#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)

#define   C_038000_TILE_MODE                           0xFFFFFF87

#define     V_038000_ARRAY_LINEAR_GENERAL              0x00000000

#define     V_038000_ARRAY_LINEAR_ALIGNED              0x00000001

#define     V_038000_ARRAY_1D_TILED_THIN1              0x00000002

#define     V_038000_ARRAY_2D_TILED_THIN1              0x00000004

#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)

#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)

#define   C_038000_TILE_TYPE                           0xFFFFFF7F
@@ -1362,6 +1366,8 @@ 
#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)

#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)

#define   C_028010_ARRAY_MODE                          0xFFF87FFF

#define     V_028010_ARRAY_1D_TILED_THIN1              0x00000002

#define     V_028010_ARRAY_2D_TILED_THIN1              0x00000004

#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)

#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)

#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF