[PATCH] skge: fix sparse warnings (7f4b45c5) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/net/skge.h

+75 −75

Original line number	Original line	Diff line number	Diff line
	@@ -532,7 +532,7 @@ enum {
	PHY_ADDR_MARV = 0,		PHY_ADDR_MARV = 0,
	};		};

	#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))		#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))

	/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */		/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
	enum {		enum {
	@@ -578,13 +578,13 @@ enum {
	MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */		MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
	MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */		MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
	MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */		MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
	#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT		MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
	};		};

	/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */		/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
	enum {		enum {
	MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */		MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
	/* Bit 14: reserved */
	MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */		MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
	MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */		MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */

	@@ -595,9 +595,10 @@ enum {
	MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */		MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
	MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */		MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
	MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */		MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */

			MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC \| (u16) MFF_ENA_TIM_PAT \| MFF_ENA_FLUSH,
	};		};

	#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC \| MFF_ENA_TIM_PAT \| MFF_ENA_FLUSH)

	/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */		/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
	/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */		/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
	@@ -1349,7 +1350,7 @@ enum {
	PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */		PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
	};		};

	#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)		#define PHY_M_PC_MDI_XMODE(x) ((((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)

	enum {		enum {
	PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */		PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
	@@ -1445,11 +1446,11 @@ enum {
	PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */		PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
	PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};		PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};

	#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */		#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
	#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */		#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
	#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */		#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */

	#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */		#define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
	/* 100=5x; 101=6x; 110=7x; 111=8x */		/* 100=5x; 101=6x; 110=7x; 111=8x */
	enum {		enum {
	MAC_TX_CLK_0_MHZ = 2,		MAC_TX_CLK_0_MHZ = 2,
	@@ -1468,6 +1469,8 @@ enum {
	PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */		PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
	/* (88E1111 only) */		/* (88E1111 only) */
	};		};
			#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
			#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)

	enum {		enum {
	PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */		PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
	@@ -1479,8 +1482,6 @@ enum {
	PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */		PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
	};		};

	#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)

	enum {		enum {
	PULS_NO_STR = 0, /* no pulse stretching */		PULS_NO_STR = 0, /* no pulse stretching */
	PULS_21MS = 1, /* 21 ms to 42 ms */		PULS_21MS = 1, /* 21 ms to 42 ms */
	@@ -1492,7 +1493,6 @@ enum {
	PULS_1300MS = 7, /* 1.3 s to 2.7 s */		PULS_1300MS = 7, /* 1.3 s to 2.7 s */
	};		};

	#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)

	enum {		enum {
	BLINK_42MS = 0, /* 42 ms */		BLINK_42MS = 0, /* 42 ms */
	@@ -2506,7 +2506,7 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
	}		}

	/* MAC Related Registers inside the device. */		/* MAC Related Registers inside the device. */
	#define SK_REG(port,reg) (((port)<<7)+(reg))		#define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
	#define SK_XMAC_REG(port, reg) \		#define SK_XMAC_REG(port, reg) \
	((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) \| (reg) << 1)		((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) \| (reg) << 1)