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Commit 7f1d8248 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: add support for dsi dynamic clock switch"

parents 209c846c 23807178

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+8 −6
Original line number Diff line number Diff line
@@ -164,10 +164,7 @@ Optional properties: 
					"dfps_immediate_porch_mode_vfp" = FPS change request is

					implemented immediately by changing panel vertical

					front porch values.

- qcom,min-refresh-rate:		Minimum refresh rate supported by the panel.

- qcom,max-refresh-rate:		Maximum refresh rate supported by the panel. If max refresh

					rate is not specified, then the frame rate of the panel in

					qcom,mdss-dsi-panel-framerate is used.

- qcom,dsi-supported-dfps-list:		List containing all the supported refresh rates.

- qcom,mdss-dsi-bl-pmic-control-type:	A string that specifies the implementation of backlight

					control for this panel.

					"bl_ctrl_pwm" = Backlight controlled by PWM gpio.
@@ -524,6 +521,10 @@ Optional properties: 
- qcom,mdss-dsi-panel-cmds-only-by-right: Boolean used to mention whether the panel support DSI1 or

					DSI0 to send commands. If this was set, that mean the panel only support

					DSI1 to send commands, otherwise DSI0 will send comands.

- qcom,dsi-dyn-clk-enable:		Boolean to indicate dsi dynamic clock switch feature

					is supported.

- qcom,dsi-dyn-clk-list:		An u32 array which lists all the supported dsi bit clock

					frequencies in Hz for the given panel.



Required properties for sub-nodes:	None

Optional properties:
@@ -645,8 +646,7 @@ Example: 
		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";

		qcom,mdss-dsi-pan-enable-dynamic-fps;

		qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";

		qcom,min-refresh-rate = <30>;

		qcom,max-refresh-rate = <60>;

		qcom,dsi-supported-dfps-list = <48 55 60>;

		qcom,mdss-dsi-bl-pmic-bank-select = <0>;

		qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>;

		qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>;
@@ -777,5 +777,7 @@ Example: 
			                <2 2 1>;

		qcom,default-topology-index = <0>;

		qcom,mdss-dsi-dma-schedule-line = <5>;

		qcom,dsi-dyn-clk-enable;

		qcom,dsi-dyn-clk-list = <798240576 801594528 804948480>;

	};

};

arch/arm64/boot/dts/qcom/qcs605-lc-sde-display.dtsi

+3 −4
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		ports {

			#address-cells = <1>;
@@ -81,7 +81,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -112,11 +112,10 @@ 
&dsi_dual_nt35597_truly_video {

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x2D>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <53 55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

arch/arm64/boot/dts/qcom/sdm670-sde-display.dtsi

+23 −27
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -160,7 +160,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -184,7 +184,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -208,7 +208,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -232,7 +232,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -250,7 +250,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -268,7 +268,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -286,7 +286,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -304,7 +304,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -322,7 +322,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -340,7 +340,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -363,7 +363,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -386,7 +386,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -408,7 +408,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -430,7 +430,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -453,7 +453,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -476,7 +476,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -499,7 +499,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -522,7 +522,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		ports {

			#address-cells = <1>;
@@ -570,11 +570,10 @@ 
&dsi_dual_nt35597_truly_video {

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x2D>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <53 55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
@@ -643,11 +642,10 @@ 
&dsi_nt35597_truly_dsc_video {

	qcom,mdss-dsi-t-clk-post = <0x0b>;

	qcom,mdss-dsi-t-clk-pre = <0x23>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <53 55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
@@ -842,11 +840,10 @@ 
&dsi_nt35695b_truly_fhd_video {

	qcom,mdss-dsi-t-clk-post = <0x07>;

	qcom,mdss-dsi-t-clk-pre = <0x1c>;

	qcom,mdss-dsi-min-refresh-rate = <48>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <48 53 55 60>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
@@ -897,11 +894,10 @@ 
&dsi_hx8399_truly_cmd {

	qcom,mdss-dsi-t-clk-post = <0x0E>;

	qcom,mdss-dsi-t-clk-pre = <0x30>;

	qcom,mdss-dsi-min-refresh-rate = <55>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+20 −22
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -139,7 +139,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -163,7 +163,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -187,7 +187,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -211,7 +211,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -234,7 +234,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -258,7 +258,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -282,7 +282,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy1>;

		clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			<&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -306,7 +306,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -324,7 +324,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -342,7 +342,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -360,7 +360,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -378,7 +378,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -396,7 +396,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -414,7 +414,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -438,7 +438,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -462,7 +462,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -486,7 +486,7 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

				<&mdss_dsi0_pll PCLK_MUX_0_CLK>;

		clock-names = "src_byte_clk", "src_pixel_clk";

		clock-names = "mux_byte_clk", "mux_pixel_clk";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -536,11 +536,10 @@ 
&dsi_dual_nt35597_truly_video {

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x2D>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <53 55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
@@ -609,11 +608,10 @@ 
&dsi_nt35597_truly_dsc_video {

	qcom,mdss-dsi-t-clk-post = <0x0b>;

	qcom,mdss-dsi-t-clk-pre = <0x23>;

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update =

		"dfps_immediate_porch_mode_vfp";

	qcom,dsi-supported-dfps-list = <53 55 60>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+10 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, 
	ctrl->ops.wait_for_cmd_mode_mdp_idle =

		dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle;

	ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk;

	ctrl->ops.wait4dynamic_refresh_done =

		dsi_ctrl_hw_cmn_wait4dynamic_refresh_done;



	switch (version) {

	case DSI_CTRL_VERSION_1_4:
@@ -218,6 +220,14 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) 
	phy->ops.clamp_ctrl = dsi_phy_hw_v3_0_clamp_ctrl;

	phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;

	phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;

	phy->ops.dyn_refresh_ops.dyn_refresh_config =

		dsi_phy_hw_v3_0_dyn_refresh_config;

	phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =

		dsi_phy_hw_v3_0_dyn_refresh_pipe_delay;

	phy->ops.dyn_refresh_ops.dyn_refresh_helper =

		dsi_phy_hw_v3_0_dyn_refresh_helper;

	phy->ops.dyn_refresh_ops.cache_phy_timings =

		dsi_phy_hw_v3_0_cache_phy_timings;

}



/**