Merge "spi: spi-geni-qcom: Introduce GSI DMA mode" (7e884b55) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/i2c/busses/i2c-qcom-geni.c

+316 −10

Original line number	Diff line number	Diff line
		@@ -26,6 +26,8 @@
		#include <linux/dma-mapping.h>
		#include <linux/qcom-geni-se.h>
		#include <linux/ipc_logging.h>
		#include <linux/dmaengine.h>
		#include <linux/msm_gpi.h>

		#define SE_I2C_TX_TRANS_LEN (0x26C)
		#define SE_I2C_RX_TRANS_LEN (0x270)
		@@ -54,6 +56,7 @@
		#define SLV_ADDR_MSK (GENMASK(15, 9))
		#define SLV_ADDR_SHFT (9)

		#define I2C_PACK_EN (BIT(0) \| BIT(1))
		#define I2C_CORE2X_VOTE (10000)
		#define GP_IRQ0 0
		#define GP_IRQ1 1
		@@ -71,6 +74,12 @@
		#define I2C_ARB_LOST GP_IRQ4
		#define DM_I2C_RX_ERR ((GP_IRQ1 \| GP_IRQ3 \| GP_IRQ4) >> 4)

		enum i2c_se_mode {
		UNINITIALIZED,
		FIFO_SE_DMA,
		GSI_ONLY,
		};

		struct geni_i2c_dev {
		struct device *dev;
		void __iomem *base;
		@@ -86,6 +95,24 @@ struct geni_i2c_dev {
		struct device *wrapper_dev;
		void *ipcl;
		int clk_fld_idx;
		struct dma_chan *tx_c;
		struct dma_chan *rx_c;
		struct msm_gpi_tre cfg0_t;
		struct msm_gpi_tre go_t;
		struct msm_gpi_tre tx_t;
		struct msm_gpi_tre rx_t;
		dma_addr_t tx_ph;
		dma_addr_t rx_ph;
		struct msm_gpi_ctrl tx_ev;
		struct msm_gpi_ctrl rx_ev;
		struct scatterlist tx_sg[5]; /* lock, cfg0, go, TX, unlock */
		struct scatterlist rx_sg;
		int cfg_sent;
		struct dma_async_tx_descriptor *tx_desc;
		struct dma_async_tx_descriptor *rx_desc;
		struct msm_gpi_dma_async_tx_cb_param tx_cb;
		struct msm_gpi_dma_async_tx_cb_param rx_cb;
		enum i2c_se_mode se_mode;
		};

		struct geni_i2c_err_log {
		@@ -184,6 +211,9 @@ static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev, "%s\n",
		gi2c_log[err].msg);
		}
		if (gi2c->se_mode == GSI_ONLY)
		goto err_out;

		if (dma) {
		rx_st = readl_relaxed(gi2c->base + SE_DMA_RX_IRQ_STAT);
		tx_st = readl_relaxed(gi2c->base + SE_DMA_TX_IRQ_STAT);
		@@ -194,6 +224,7 @@ static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
		GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
		"DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
		dma, tx_st, rx_st, m_stat);
		err_out:
		GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
		"m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
		m_cmd, geni_s, geni_ios);
		@@ -305,6 +336,258 @@ static irqreturn_t geni_i2c_irq(int irq, void *dev)
		return IRQ_HANDLED;
		}

		static void gi2c_ev_cb(struct dma_chan ch, struct msm_gpi_cb const cb_str,
		void *ptr)
		{
		struct geni_i2c_dev *gi2c = ptr;
		u32 m_stat = cb_str->status;

		switch (cb_str->cb_event) {
		case MSM_GPI_QUP_ERROR:
		case MSM_GPI_QUP_SW_ERROR:
		case MSM_GPI_QUP_MAX_EVENT:
		/* fall through to stall impacted channel */
		case MSM_GPI_QUP_CH_ERROR:
		case MSM_GPI_QUP_PENDING_EVENT:
		case MSM_GPI_QUP_EOT_DESC_MISMATCH:
		break;
		case MSM_GPI_QUP_NOTIFY:
		if (m_stat & M_GP_IRQ_1_EN)
		geni_i2c_err(gi2c, I2C_NACK);
		if (m_stat & M_GP_IRQ_3_EN)
		geni_i2c_err(gi2c, I2C_BUS_PROTO);
		if (m_stat & M_GP_IRQ_4_EN)
		geni_i2c_err(gi2c, I2C_ARB_LOST);
		complete(&gi2c->xfer);
		break;
		default:
		break;
		}
		if (cb_str->cb_event != MSM_GPI_QUP_NOTIFY)
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"GSI QN err:0x%x, status:0x%x, err:%d\n",
		cb_str->error_log.error_code,
		m_stat, cb_str->cb_event);
		}

		static void gi2c_gsi_tx_cb(void *ptr)
		{
		struct msm_gpi_dma_async_tx_cb_param *tx_cb = ptr;
		struct geni_i2c_dev *gi2c = tx_cb->userdata;

		if (!(gi2c->cur->flags & I2C_M_RD))
		complete(&gi2c->xfer);
		}

		static void gi2c_gsi_rx_cb(void *ptr)
		{
		struct msm_gpi_dma_async_tx_cb_param *rx_cb = ptr;
		struct geni_i2c_dev *gi2c = rx_cb->userdata;

		if (gi2c->cur->flags & I2C_M_RD) {
		if (rx_cb->status & DM_I2C_RX_ERR) {
		GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
		"RX TCE Unexpected Err, stat:0x%x\n",
		rx_cb->status);
		if (rx_cb->status & GP_IRQ1)
		geni_i2c_err(gi2c, I2C_NACK);
		if (rx_cb->status & GP_IRQ3)
		geni_i2c_err(gi2c, I2C_BUS_PROTO);
		if (rx_cb->status & GP_IRQ4)
		geni_i2c_err(gi2c, I2C_ARB_LOST);
		}
		complete(&gi2c->xfer);
		}
		}

		static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
		int num)
		{
		struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
		int i, ret = 0, timeout = 0;

		if (!gi2c->tx_c) {
		gi2c->tx_c = dma_request_slave_channel(gi2c->dev, "tx");
		if (!gi2c->tx_c) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"tx dma req slv chan ret :%d\n", ret);
		return -EIO;
		}
		gi2c->tx_ev.init.callback = gi2c_ev_cb;
		gi2c->tx_ev.init.cb_param = gi2c;
		gi2c->tx_ev.cmd = MSM_GPI_INIT;
		gi2c->tx_c->private = &gi2c->tx_ev;
		ret = dmaengine_slave_config(gi2c->tx_c, NULL);
		if (ret) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"tx dma slave config ret :%d\n", ret);
		return ret;
		}
		}
		if (!gi2c->rx_c) {
		gi2c->rx_c = dma_request_slave_channel(gi2c->dev, "rx");
		if (!gi2c->rx_c) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"rx dma req slv chan ret :%d\n", ret);
		return -EIO;
		}
		gi2c->rx_ev.init.cb_param = gi2c;
		gi2c->rx_ev.init.callback = gi2c_ev_cb;
		gi2c->rx_ev.cmd = MSM_GPI_INIT;
		gi2c->rx_c->private = &gi2c->rx_ev;
		ret = dmaengine_slave_config(gi2c->rx_c, NULL);
		if (ret) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"rx dma slave config ret :%d\n", ret);
		return ret;
		}
		}

		if (!gi2c->cfg_sent) {
		struct geni_i2c_clk_fld *itr = geni_i2c_clk_map +
		gi2c->clk_fld_idx;
		struct msm_gpi_tre *cfg0 = &gi2c->cfg0_t;

		/* config0 */
		cfg0->dword[0] = MSM_GPI_I2C_CONFIG0_TRE_DWORD0(I2C_PACK_EN,
		itr->t_cycle,
		itr->t_high,
		itr->t_low);
		cfg0->dword[1] = MSM_GPI_I2C_CONFIG0_TRE_DWORD1(0, 0);
		cfg0->dword[2] = MSM_GPI_I2C_CONFIG0_TRE_DWORD2(0,
		itr->clk_div);
		cfg0->dword[3] = MSM_GPI_I2C_CONFIG0_TRE_DWORD3(0, 0, 0, 1);

		gi2c->tx_cb.userdata = gi2c;
		gi2c->rx_cb.userdata = gi2c;
		}

		for (i = 0; i < num; i++) {
		u8 op = (msgs[i].flags & I2C_M_RD) ? 2 : 1;
		int segs = 3 - op;
		int index = 0;
		int stretch = (i < (num - 1));
		dma_cookie_t tx_cookie, rx_cookie;
		struct msm_gpi_tre *go_t = &gi2c->go_t;
		struct device *rx_dev = gi2c->rx_c->device->dev;
		struct device *tx_dev = gi2c->tx_c->device->dev;

		gi2c->cur = &msgs[i];
		if (!gi2c->cfg_sent) {
		segs++;
		sg_init_table(gi2c->tx_sg, segs);
		sg_set_buf(gi2c->tx_sg, &gi2c->cfg0_t,
		sizeof(gi2c->cfg0_t));
		gi2c->cfg_sent = 1;
		index++;
		} else {
		sg_init_table(gi2c->tx_sg, segs);
		}

		go_t->dword[0] = MSM_GPI_I2C_GO_TRE_DWORD0((stretch << 2),
		msgs[i].addr, op);
		go_t->dword[1] = MSM_GPI_I2C_GO_TRE_DWORD1;

		if (msgs[i].flags & I2C_M_RD) {
		go_t->dword[2] = MSM_GPI_I2C_GO_TRE_DWORD2(msgs[i].len);
		go_t->dword[3] = MSM_GPI_I2C_GO_TRE_DWORD3(0, 0, 1, 0);
		} else {
		go_t->dword[2] = MSM_GPI_I2C_GO_TRE_DWORD2(0);
		go_t->dword[3] = MSM_GPI_I2C_GO_TRE_DWORD3(0, 0, 0, 1);
		}

		sg_set_buf(&gi2c->tx_sg[index++], &gi2c->go_t,
		sizeof(gi2c->go_t));

		if (msgs[i].flags & I2C_M_RD) {
		sg_init_table(&gi2c->rx_sg, 1);
		gi2c->rx_ph = dma_map_single(rx_dev, msgs[i].buf,
		msgs[i].len,
		DMA_FROM_DEVICE);
		gi2c->rx_t.dword[0] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(gi2c->rx_ph);
		gi2c->rx_t.dword[1] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(gi2c->rx_ph);
		gi2c->rx_t.dword[2] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(msgs[i].len);
		gi2c->rx_t.dword[3] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, 1, 0, 0);

		sg_set_buf(&gi2c->rx_sg, &gi2c->rx_t,
		sizeof(gi2c->rx_t));
		gi2c->rx_desc = dmaengine_prep_slave_sg(gi2c->rx_c,
		&gi2c->rx_sg, 1,
		DMA_DEV_TO_MEM,
		(DMA_PREP_INTERRUPT \|
		DMA_CTRL_ACK));
		if (!gi2c->rx_desc) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"prep_slave_sg for rx failed\n");
		gi2c->err = -ENOMEM;
		return gi2c->err;
		}
		gi2c->rx_desc->callback = gi2c_gsi_rx_cb;
		gi2c->rx_desc->callback_param = &gi2c->rx_cb;

		/* Issue RX */
		rx_cookie = dmaengine_submit(gi2c->rx_desc);
		dma_async_issue_pending(gi2c->rx_c);
		} else {
		gi2c->tx_ph = dma_map_single(tx_dev, msgs[i].buf,
		msgs[i].len,
		DMA_TO_DEVICE);
		gi2c->tx_t.dword[0] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(gi2c->tx_ph);
		gi2c->tx_t.dword[1] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(gi2c->tx_ph);
		gi2c->tx_t.dword[2] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(msgs[i].len);
		gi2c->tx_t.dword[3] =
		MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, 1, 0, 0);

		sg_set_buf(&gi2c->tx_sg[index++], &gi2c->tx_t,
		sizeof(gi2c->tx_t));
		}

		gi2c->tx_desc = dmaengine_prep_slave_sg(gi2c->tx_c, gi2c->tx_sg,
		segs, DMA_MEM_TO_DEV,
		(DMA_PREP_INTERRUPT \|
		DMA_CTRL_ACK));
		if (!gi2c->tx_desc) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"prep_slave_sg for tx failed\n");
		gi2c->err = -ENOMEM;
		return gi2c->err;
		}
		gi2c->tx_desc->callback = gi2c_gsi_tx_cb;
		gi2c->tx_desc->callback_param = &gi2c->tx_cb;

		/* Issue TX */
		tx_cookie = dmaengine_submit(gi2c->tx_desc);
		dma_async_issue_pending(gi2c->tx_c);

		timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);
		if (msgs[i].flags & I2C_M_RD)
		dma_unmap_single(rx_dev, gi2c->rx_ph, msgs[i].len,
		DMA_FROM_DEVICE);
		else
		dma_unmap_single(tx_dev, gi2c->tx_ph, msgs[i].len,
		DMA_TO_DEVICE);

		if (!timeout) {
		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
		"GSI Txn timed out\n");
		gi2c->err = -ETIMEDOUT;
		}
		if (gi2c->err) {
		dmaengine_terminate_all(gi2c->tx_c);
		gi2c->cfg_sent = 0;
		return gi2c->err;
		}
		}
		return gi2c->err;
		}

		static int geni_i2c_xfer(struct i2c_adapter *adap,
		struct i2c_msg msgs[],
		int num)
		@@ -324,6 +607,11 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
		pm_runtime_set_suspended(gi2c->dev);
		return ret;
		}
		if (gi2c->se_mode == GSI_ONLY) {
		ret = geni_i2c_gsi_xfer(adap, msgs, num);
		goto geni_i2c_txn_ret;
		}

		qcom_geni_i2c_conf(gi2c, 0);
		dev_dbg(gi2c->dev, "i2c xfer:num:%d, msgs:len:%d,flg:%d\n",
		num, msgs[0].len, msgs[0].flags);
		@@ -418,8 +706,9 @@ static int geni_i2c_xfer(struct i2c_adapter *adap,
		break;
		}
		}
		geni_i2c_txn_ret:
		if (ret == 0)
		ret = i;
		ret = num;
		pm_runtime_put_sync(gi2c->dev);
		gi2c->cur = NULL;
		gi2c->err = 0;
		@@ -592,7 +881,9 @@ static int geni_i2c_runtime_suspend(struct device *dev)
		{
		struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);

		if (gi2c->se_mode == FIFO_SE_DMA)
		disable_irq(gi2c->irq);

		se_geni_resources_off(&gi2c->i2c_rsc);
		return 0;
		}
		@@ -612,16 +903,31 @@ static int geni_i2c_runtime_resume(struct device *dev)
		if (ret)
		return ret;

		if (unlikely(!gi2c->tx_wm)) {
		if (gi2c->se_mode == UNINITIALIZED) {
		u32 se_mode = readl_relaxed(gi2c->base +
		GENI_IF_FIFO_DISABLE_RO);

		if (se_mode) {
		gi2c->se_mode = GSI_ONLY;
		geni_se_select_mode(gi2c->base, GSI_DMA);
		GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
		"i2c in GSI ONLY mode\n");
		} else {
		int gi2c_tx_depth = get_tx_fifo_depth(gi2c->base);

		gi2c->se_mode = FIFO_SE_DMA;

		gi2c->tx_wm = gi2c_tx_depth - 1;
		geni_se_init(gi2c->base, gi2c->tx_wm, gi2c_tx_depth);
		se_config_packing(gi2c->base, 8, 4, true);
		GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
		"i2c fifo depth:%d\n", gi2c_tx_depth);
		"i2c fifo/se-dma mode. fifo depth:%d\n",
		gi2c_tx_depth);
		}
		}
		if (gi2c->se_mode == FIFO_SE_DMA)
		enable_irq(gi2c->irq);

		return 0;
		}

drivers/platform/msm/qcom-geni-se.c

+15 −4

Original line number	Diff line number	Diff line
		@@ -293,20 +293,31 @@ static int geni_se_select_dma_mode(void __iomem *base)

		static int geni_se_select_gsi_mode(void __iomem *base)
		{
		unsigned int io_mode = 0;
		unsigned int geni_dma_mode = 0;
		unsigned int gsi_event_en = 0;
		unsigned int common_geni_m_irq_en = 0;
		unsigned int common_geni_s_irq_en = 0;

		common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN);
		common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN);
		common_geni_m_irq_en &=
		~(M_CMD_DONE_EN \| M_TX_FIFO_WATERMARK_EN \|
		M_RX_FIFO_WATERMARK_EN \| M_RX_FIFO_LAST_EN);
		common_geni_s_irq_en &= ~S_CMD_DONE_EN;
		geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN);
		gsi_event_en = geni_read_reg(base, SE_GSI_EVENT_EN);
		io_mode = geni_read_reg(base, SE_IRQ_EN);

		geni_dma_mode \|= GENI_DMA_MODE_EN;
		io_mode &= ~(DMA_TX_IRQ_EN \| DMA_RX_IRQ_EN);
		gsi_event_en \|= (DMA_RX_EVENT_EN \| DMA_TX_EVENT_EN \|
		GENI_M_EVENT_EN \| GENI_S_EVENT_EN);

		geni_write_reg(io_mode, base, SE_IRQ_EN);
		geni_write_reg(0, base, SE_IRQ_EN);
		geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN);
		geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN);
		geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR);
		geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR);
		geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR);
		geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR);
		geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN);
		geni_write_reg(gsi_event_en, base, SE_GSI_EVENT_EN);
		return 0;

drivers/spi/spi-geni-qcom.c

+635 −70

File changed.

Preview size limit exceeded, changes collapsed.

include/linux/qcom-geni-se.h

+9 −2

Original line number	Diff line number	Diff line
		@@ -82,7 +82,7 @@ struct se_geni_rsc {
		#define GENI_SER_M_CLK_CFG (0x48)
		#define GENI_SER_S_CLK_CFG (0x4C)
		#define GENI_CLK_CTRL_RO (0x60)
		#define GENI_IF_DISABLE_RO (0x64)
		#define GENI_IF_FIFO_DISABLE_RO (0x64)
		#define GENI_FW_REVISION_RO (0x68)
		#define GENI_FW_S_REVISION_RO (0x6C)
		#define SE_GENI_CLK_SEL (0x7C)
		@@ -147,7 +147,8 @@ struct se_geni_rsc {

		/* CLK_CTRL_RO fields */

		/* IF_DISABLE_RO fields */
		/* FIFO_IF_DISABLE_RO fields */
		#define FIFO_IF_DISABLE (BIT(0))

		/* FW_REVISION_RO fields */
		#define FW_REV_PROTOCOL_MSK (GENMASK(15, 8))
		@@ -330,6 +331,12 @@ struct se_geni_rsc {
		#define DEFAULT_BUS_WIDTH (4)
		#define DEFAULT_SE_CLK (19200000)

		/* GSI TRE fields */
		/* Packing fields */
		#define GSI_TX_PACK_EN (BIT(0))
		#define GSI_RX_PACK_EN (BIT(1))
		#define GSI_PRESERVE_PACK (BIT(2))

		#define GENI_SE_ERR(log_ctx, print, dev, x...) do { \
		if (log_ctx) \
		ipc_log_string(log_ctx, x); \