Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7e3bfc7c authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Handle IDE PIO cache aliases on SMP. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bb12d612

arch/mips/mm/c-r3k.c

+5 −0
Original line number Diff line number Diff line
@@ -260,6 +260,10 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, 
{

}



static void local_r3k_flush_data_cache_page(unsigned long addr)

{

}



static void r3k_flush_data_cache_page(unsigned long addr)

{

}
@@ -335,6 +339,7 @@ void __init r3k_cache_init(void) 
	flush_icache_range = r3k_flush_icache_range;



	flush_cache_sigtramp = r3k_flush_cache_sigtramp;

	local_flush_data_cache_page = local_r3k_flush_data_cache_page;

	flush_data_cache_page = r3k_flush_data_cache_page;



	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;

arch/mips/mm/c-r4k.c

+1 −0
Original line number Diff line number Diff line
@@ -1199,6 +1199,7 @@ void __init r4k_cache_init(void) 


	flush_cache_sigtramp	= r4k_flush_cache_sigtramp;

	flush_icache_all	= r4k_flush_icache_all;

	local_flush_data_cache_page	= local_r4k_flush_data_cache_page;

	flush_data_cache_page	= r4k_flush_data_cache_page;

	flush_icache_range	= r4k_flush_icache_range;

arch/mips/mm/c-sb1.c

+1 −0
Original line number Diff line number Diff line
@@ -528,6 +528,7 @@ void sb1_cache_init(void) 
	flush_cache_page = sb1_flush_cache_page;



	flush_cache_sigtramp = sb1_flush_cache_sigtramp;

	local_flush_data_cache_page = (void *) sb1_nop;

	flush_data_cache_page = (void *) sb1_nop;



	/* Full flush */

arch/mips/mm/c-tx39.c

+7 −0
Original line number Diff line number Diff line
@@ -216,6 +216,11 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page 
		tx39_blast_icache_page_indexed(page);

}



static void local_tx39_flush_data_cache_page(void * addr)

{

	tx39_blast_dcache_page(addr);

}



static void tx39_flush_data_cache_page(unsigned long addr)

{

	tx39_blast_dcache_page(addr);
@@ -381,6 +386,7 @@ void __init tx39_cache_init(void) 
		flush_icache_range	= (void *) tx39h_flush_icache_all;



		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;

		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;

		flush_data_cache_page	= (void *) tx39h_flush_icache_all;



		_dma_cache_wback_inv	= tx39h_dma_cache_wback_inv;
@@ -406,6 +412,7 @@ void __init tx39_cache_init(void) 
		flush_icache_range = tx39_flush_icache_range;



		flush_cache_sigtramp = tx39_flush_cache_sigtramp;

		local_flush_data_cache_page = local_tx39_flush_data_cache_page;

		flush_data_cache_page = tx39_flush_data_cache_page;



		_dma_cache_wback_inv = tx39_dma_cache_wback_inv;

arch/mips/mm/cache.c

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); 


/* MIPS specific cache operations */

void (*flush_cache_sigtramp)(unsigned long addr);

void (*local_flush_data_cache_page)(void * addr);

void (*flush_data_cache_page)(unsigned long addr);

void (*flush_icache_all)(void);