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Commit 7de970e1 authored by Nate Dailey's avatar Nate Dailey Committed by Jeff Garzik
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sata_vsc: use default cache line size if non-zero 



This modifies drivers/ata/sata_vsc.c to only set the cache line size
to 0x80 if the default value is zero. Apparently zero isn't allowed
due to a bug in the chip, but I've found performance is much better
with the (non-zero) default instead of 0x80.

[note1: "default" means BIOS-programmed value, in this context -jgarzik]

[note2: superfluous braces were removed from the patch -jg]

Signed-off-by: default avatarNate Dailey <nate.dailey@stratus.com>
Signed-off-by: default avatarJeremy Higdon <jeremy@sgi.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 5278b50c

drivers/ata/sata_vsc.c

+6 −2
Original line number Diff line number Diff line
@@ -346,6 +346,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d 
	struct ata_probe_ent *probe_ent;

	void __iomem *mmio_base;

	int rc;

	u8 cls;



	if (!printed_version++)

		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
@@ -383,8 +384,11 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d 
	INIT_LIST_HEAD(&probe_ent->node);



	/*

	 * Due to a bug in the chip, the default cache line size can't be used

	 * Due to a bug in the chip, the default cache line size can't be

	 * used (unless the default is non-zero).

	 */

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);

	if (cls == 0x00)

		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);



	if (pci_enable_msi(pdev) == 0)