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Commit 7d8e18e4 authored by Arend van Spriel's avatar Arend van Spriel Committed by John W. Linville
Browse files

brcm80211: smac: replace ai_corereg() function with ai_cc_reg()



The ai_corereg() function is only used in the driver to safely
access the chipcommon core. The function has been renamed to
ai_cc_reg() removing the need to provide a core index parameter.

Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: default avatarAlwin Beukers <alwin@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarFranky Lin <frankyl@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent ad5db131
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+13 −23
Original line number Diff line number Diff line
@@ -885,7 +885,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
	w = getintvar(sih, BRCMS_SROM_LEDDC);
	if (w == 0)
		w = DEFAULT_GPIOTIMERVAL;
	ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval),
	ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
		  ~0, w);

	if (PCIE(sih))
@@ -898,8 +898,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
		 */
		if (ai_get_chiprev(sih) == 0) {
			SI_MSG("Applying 43224A0 WARs\n");
			ai_corereg(sih, SI_CC_IDX,
				   offsetof(struct chipcregs, chipcontrol),
			ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
				  CCTRL43224_GPIO_TOGGLE,
				  CCTRL43224_GPIO_TOGGLE);
			si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
@@ -1104,40 +1103,31 @@ void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
 * Also, when using pci/pcie, we can optimize away the core switching for pci
 * registers and (on newer pci cores) chipcommon registers.
 */
uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
		uint val)
uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
{
	struct bcma_device *cc;
	uint origidx = 0;
	u32 __iomem *r = NULL;
	uint w;
	u32 w;
	uint intr_val = 0;
	struct si_info *sii;

	sii = (struct si_info *)sih;

	if (coreidx >= SI_MAXCORES)
		return 0;
	cc = sii->icbus->drv_cc.core;

	INTR_OFF(sii, intr_val);

	/* save current core index */
	origidx = ai_coreidx(&sii->pub);

	/* switch core */
	r = (u32 __iomem *) ((unsigned char __iomem *)
		ai_setcoreidx(&sii->pub, coreidx) + regoff);

	/* mask and set */
	if (mask || val) {
		w = (R_REG(r) & ~mask) | val;
		W_REG(r, w);
		bcma_maskset32(cc, regoff, ~mask, val);
	}

	/* readback */
	w = R_REG(r);
	w = bcma_read32(cc, regoff);

	/* restore core index */
	if (origidx != coreidx)
	ai_setcoreidx(&sii->pub, origidx);

	INTR_RESTORE(sii, intr_val);
@@ -1664,7 +1654,7 @@ u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
	uint regoff;

	regoff = offsetof(struct chipcregs, gpiocontrol);
	return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
	return ai_cc_reg(sih, regoff, mask, val);
}

void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
+1 −4
Original line number Diff line number Diff line
@@ -228,8 +228,6 @@ extern bool ai_iscoreup(struct si_pub *sih);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
		       uint val);
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(struct si_pub *sih, u32 bits);
extern int ai_numaddrspaces(struct si_pub *sih);
@@ -242,8 +240,7 @@ extern struct si_pub *ai_attach(struct bcma_bus *pbus);
extern void ai_detach(struct si_pub *sih);
extern uint ai_coreid(struct si_pub *sih);
extern uint ai_corerev(struct si_pub *sih);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
		uint val);
extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
+8 −8
Original line number Diff line number Diff line
@@ -1709,17 +1709,17 @@ void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
{
	BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);

	ai_corereg(wlc_hw->sih, SI_CC_IDX,
		   offsetof(struct chipcregs, chipcontrol_addr), ~0, 0);
	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
		  ~0, 0);
	udelay(1);
	ai_corereg(wlc_hw->sih, SI_CC_IDX,
		   offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
		  0x4, 0);
	udelay(1);
	ai_corereg(wlc_hw->sih, SI_CC_IDX,
		   offsetof(struct chipcregs, chipcontrol_data), 0x4, 4);
	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
		  0x4, 4);
	udelay(1);
	ai_corereg(wlc_hw->sih, SI_CC_IDX,
		   offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
		  0x4, 0);
	udelay(1);
}

+14 −14
Original line number Diff line number Diff line
@@ -530,10 +530,10 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
	case SI_PCIDOWN:
		/* turn on serdes PLL down */
		if (ai_get_buscorerev(sih) == 6) {
			ai_corereg(sih, SI_CC_IDX,
			ai_cc_reg(sih,
				  offsetof(struct chipcregs, chipcontrol_addr),
				  ~0, 0);
			ai_corereg(sih, SI_CC_IDX,
			ai_cc_reg(sih,
				  offsetof(struct chipcregs, chipcontrol_data),
				  ~0x40, 0);
		} else if (pi->pcie_pr42767) {
@@ -543,10 +543,10 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
	case SI_PCIUP:
		/* turn off serdes PLL down */
		if (ai_get_buscorerev(sih) == 6) {
			ai_corereg(sih, SI_CC_IDX,
			ai_cc_reg(sih,
				  offsetof(struct chipcregs, chipcontrol_addr),
				  ~0, 0);
			ai_corereg(sih, SI_CC_IDX,
			ai_cc_reg(sih,
				  offsetof(struct chipcregs, chipcontrol_data),
				  ~0x40, 0x40);
		} else if (PCIE_ASPM(sih)) {	/* disable clkreq */
@@ -666,7 +666,7 @@ static void pcie_war_noplldown(struct pcicore_info *pi)
	u16 __iomem *reg16;

	/* turn off serdes PLL down */
	ai_corereg(pi->sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol),
	ai_cc_reg(pi->sih, offsetof(struct chipcregs, chipcontrol),
		  CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);

	/* clear srom shadow backdoor */
+18 −18
Original line number Diff line number Diff line
@@ -2905,27 +2905,27 @@ void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
				mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);

			}
			ai_corereg(pi->sh->sih, SI_CC_IDX,
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpiocontrol),
				  ~0x0, 0x0);
			ai_corereg(pi->sh->sih, SI_CC_IDX,
				   offsetof(struct chipcregs, gpioout), 0x40,
				   0x40);
			ai_corereg(pi->sh->sih, SI_CC_IDX,
				   offsetof(struct chipcregs, gpioouten), 0x40,
				   0x40);
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpioout),
				  0x40, 0x40);
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpioouten),
				  0x40, 0x40);
		} else {
			mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);

			mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);

			ai_corereg(pi->sh->sih, SI_CC_IDX,
				   offsetof(struct chipcregs, gpioout), 0x40,
				   0x00);
			ai_corereg(pi->sh->sih, SI_CC_IDX,
				   offsetof(struct chipcregs, gpioouten), 0x40,
				   0x0);
			ai_corereg(pi->sh->sih, SI_CC_IDX,
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpioout),
				  0x40, 0x00);
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpioouten),
				  0x40, 0x0);
			ai_cc_reg(pi->sh->sih,
				  offsetof(struct chipcregs, gpiocontrol),
				  ~0x0, 0x40);
		}
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