Commit 7c7730bb authored Apr 14, 2017 by Deepak Katragadda

ARM: dts: msm: Correct the register offset for clock_dispcc on SDM845



The register offset being used for the display clock controller
is incorrect. Fix it.

Change-Id: I6edce7e8440021102311f3bba203ae1f90a08d54
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

parent e4e90297

arch/arm64/boot/dts/qcom/sdm845.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -830,7 +830,7 @@

		clock_dispcc: qcom,dispcc@af00000 {
		compatible = "qcom,dispcc-sdm845", "syscon";
		reg = <0xaf00000 0x100000>;
		reg = <0xaf00000 0x10000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		#clock-cells = <1>;