Merge "msm: camera: Add reset logic for snps phy" (7bea3181) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -28,6 +28,9 @@
		#define mask_enable_clk_B 0x2
		#define mask_ctrl_1_A 0x5
		#define mask_ctrl_1_B 0xA
		#define mask_reset_A 0x1
		#define mask_reset_B 0x7
		#define mask_shutdown_A 0x3
		#define mask_hs_freq_range 0x7F
		#define mask_osc_freq_2 0xFF
		#define mask_osc_freq_3 0xF00
		@@ -56,8 +59,6 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = {
		{0x58C, 0xFF}, /* mipi_csiphy_irq_mask_ctrl_lane_0 */
		{0x5C8, 0xFF}, /* mipi_csiphy_irq_mask_ctrl_lane_clk_0 */
		{0x20, 0x0}, /* mipi_csiphy_rx_sys_7_00 */
		{0x28, 0x43}, /* mipi_csiphy_rx_sys_9_00 */
		{0x380, 0x0}, /* mipi_csiphy_rx_startup_ovr_0_00 */
		{0x384, 0x0}, /* mipi_csiphy_rx_startup_ovr_1_00 */
		{0x388, 0xCC}, /* mipi_csiphy_rx_startup_ovr_2_00 */
		{0x38C, 0x1}, /* mipi_csiphy_rx_startup_ovr_3_00 */

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+106 −40

Original line number	Diff line number	Diff line
		@@ -252,10 +252,13 @@ static int msm_csiphy_snps_2_lane_config(
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_sys_7_00.addr + offset);

		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_sys_9_00.data,
		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_clk_lane_6_00.addr + offset);
		value \|= SET_THE_BIT(7);
		msm_camera_io_w(value,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_sys_9_00.addr + offset);
		mipi_csiphy_rx_clk_lane_6_00.addr + offset);

		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_ovr_4_00.data,
		@@ -317,7 +320,7 @@ static int msm_csiphy_snps_lane_config(
		uint16_t lane_mask = 0;
		void __iomem *csiphybase;
		enum snps_csiphy_mode mode = INVALID_MODE;
		uint32_t value, num_tries, num_lanes, offset;
		uint32_t value, num_tries, num_lanes, offset = SNPS_INTERPHY_OFFSET;
		uint32_t clk_mux_reg = 0;

		csiphybase = csiphy_dev->base;
		@@ -495,17 +498,6 @@ static int msm_csiphy_snps_lane_config(
		mipi_csiphy_rx_clk_lane_7_00.addr +
		SNPS_INTERPHY_OFFSET);

		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_ovr_0_00.addr +
		SNPS_INTERPHY_OFFSET);
		value \|= SET_THE_BIT(0);
		value \|= SET_THE_BIT(1);
		msm_camera_io_w(value,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_ovr_0_00.addr +
		SNPS_INTERPHY_OFFSET);

		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_ovr_1_00.addr +
		@@ -521,6 +513,7 @@ static int msm_csiphy_snps_lane_config(
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_clk_lane_6_00.addr);
		value \|= SET_THE_BIT(2);
		value &= ~(SET_THE_BIT(7));
		msm_camera_io_w(value,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_clk_lane_6_00.addr);
		@@ -530,7 +523,7 @@ static int msm_csiphy_snps_lane_config(
		mipi_csiphy_rx_clk_lane_6_00.addr +
		SNPS_INTERPHY_OFFSET);
		value \|= SET_THE_BIT(3);
		value \|= SET_THE_BIT(7);
		value &= ~(SET_THE_BIT(7));
		value &= ~(SET_THE_BIT(2));
		msm_camera_io_w(value,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		@@ -592,19 +585,41 @@ static int msm_csiphy_snps_lane_config(
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_enable_clk.addr);

		if (mode == TWO_LANE_PHY_A) {
		msm_camera_io_w(mask_reset_A,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		msm_camera_io_w(mask_ctrl_1_A,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		value = 0x0;
		if (mode == AGGREGATE_MODE \|\| mode == TWO_LANE_PHY_A)
		value \|= mask_ctrl_1_A;
		if (mode == AGGREGATE_MODE \|\| mode == TWO_LANE_PHY_B)
		value \|= mask_ctrl_1_B;
		msm_camera_io_w(value,
		num_tries = 0;

		do {
		num_tries++;
		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_obs_2_00.addr);
		if ((value \| SET_THE_BIT(4)) == value)
		break;
		usleep_range(100, 150);
		} while (num_tries < 6);
		if ((value \| SET_THE_BIT(4)) != value) {
		pr_err("%s: SNPS phy config failed\n", __func__);
		return -EINVAL;
		}
		}

		if (mode == TWO_LANE_PHY_B) {
		msm_camera_io_w(mask_reset_B,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		if (mode == AGGREGATE_MODE \|\| mode == TWO_LANE_PHY_A)
		offset = 0x0;
		else
		offset = SNPS_INTERPHY_OFFSET;
		msm_camera_io_w(mask_ctrl_1_A\|mask_ctrl_1_B,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		value = 0x0;
		num_tries = 0;
		@@ -623,6 +638,57 @@ static int msm_csiphy_snps_lane_config(
		pr_err("%s: SNPS phy config failed\n", __func__);
		return -EINVAL;
		}
		}

		if (mode == AGGREGATE_MODE) {
		msm_camera_io_w(mask_shutdown_A,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		msm_camera_io_w(mask_reset_B,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		value = 0x0;
		num_tries = 0;

		do {
		num_tries++;
		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_obs_2_00.addr);
		if ((value \| SET_THE_BIT(4)) == value)
		break;
		usleep_range(100, 150);
		} while (num_tries < 6);

		if ((value \| SET_THE_BIT(4)) != value) {
		pr_err("%s: SNPS phy config failed\n", __func__);
		return -EINVAL;
		}

		msm_camera_io_w(mask_ctrl_1_A\|mask_ctrl_1_B,
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_ctrl_1.addr);

		value = 0x0;
		num_tries = 0;

		do {
		num_tries++;
		value = msm_camera_io_r(csiphybase +
		csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_rx_startup_obs_2_00.addr + offset);
		if ((value \| SET_THE_BIT(4)) == value)
		break;
		usleep_range(100, 150);
		} while (num_tries < 6);

		if ((value \| SET_THE_BIT(4)) != value) {
		pr_err("%s: SNPS phy config failed\n", __func__);
		return -EINVAL;
		}
		}

		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg.
		mipi_csiphy_force_mode.data,

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h

+0 −2

Original line number	Diff line number	Diff line
		@@ -83,8 +83,6 @@ struct csiphy_reg_snps_parms_t {
		struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_0;
		struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_clk_0;
		struct csiphy_reg_t mipi_csiphy_rx_sys_7_00;
		struct csiphy_reg_t mipi_csiphy_rx_sys_9_00;
		struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_0_00;
		struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_1_00;
		struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_2_00;
		struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_3_00;