Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7b27254a authored by Mukesh Kumar Savaliya's avatar Mukesh Kumar Savaliya
Browse files

ARM: dts: msm: Enable serial engines for CDP/MTP on sdm670 



Enable console UART, I2C and SPI instances of QUPv3 SE [Serial Engine]
for the internal platforms.

Change-Id: I6b8a5832ab9004653ba0d249f37b20854d69b155
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent 4d9a308b

arch/arm64/boot/dts/qcom/sdm670-cdp.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -9,3 +9,27 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&qupv3_se9_2uart {

	status = "disabled";

};



&qupv3_se12_2uart {

	status = "ok";

};



&qupv3_se8_spi {

	status = "disabled";

};



&qupv3_se3_i2c {

	status = "disabled";

};



&qupv3_se10_i2c {

	status = "disabled";

};



&qupv3_se6_4uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/sdm670-mtp.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -9,3 +9,27 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&qupv3_se9_2uart {

	status = "disabled";

};



&qupv3_se12_2uart {

	status = "ok";

};



&qupv3_se8_spi {

	status = "disabled";

};



&qupv3_se3_i2c {

	status = "disabled";

};



&qupv3_se10_i2c {

	status = "disabled";

};



&qupv3_se6_4uart {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -904,6 +904,34 @@ 
			};

		};



		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {

			qupv3_se12_2uart_active: qupv3_se12_2uart_active {

				mux {

					pins = "gpio51", "gpio52";

					function = "qup9";

				};



				config {

					pins = "gpio51", "gpio52";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep {

				mux {

					pins = "gpio51", "gpio52";

					function = "gpio";

				};



				config {

					pins = "gpio51", "gpio52";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se12_spi_pins: qupv3_se12_spi_pins {

			qupv3_se12_spi_active: qupv3_se12_spi_active {

				mux {

arch/arm64/boot/dts/qcom/sdm670-qupv3.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -407,6 +407,23 @@ 
		status = "disabled";

	};



	/* Debug UART Instance for CDP/MTP platform on SDM670 */

	qupv3_se12_2uart: qcom,qup_uart@0xa90000 {

		compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart";

		reg = <0xa90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se12_2uart_active>;

		pinctrl-1 = <&qupv3_se12_2uart_sleep>;

		interrupts = <GIC_SPI 357 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se8_i2c: i2c@a80000 {

		compatible = "qcom,i2c-geni";

arch/arm64/boot/dts/qcom/sdm670.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -32,6 +32,14 @@ 
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

	};



	aliases {

		serial0 = &qupv3_se12_2uart;

		spi0 = &qupv3_se8_spi;

		i2c0 = &qupv3_se10_i2c;

		i2c1 = &qupv3_se3_i2c;

		hsuart0 = &qupv3_se6_4uart;

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;