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Commit 7b24f280 authored by Casey Piper's avatar Casey Piper Committed by Narendra Muppalla
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clk: msm: mdss: update HDMI PLL locking sequence for MSM8996v1 



Update SVS mode and driver level settings for
MSM8996v1 PLL locking sequence, based on Si
characterization.

Change-Id: Ic25e89f62b222847eef491a1c4138434ab2b38fe
Signed-off-by: default avatarCasey Piper <cpiper@codeaurora.org>
parent 8d722061

drivers/clk/qcom/mdss/mdss-hdmi-pll-8996.c

+41 −20
Original line number Diff line number Diff line
@@ -739,7 +739,8 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, 
	cfg->com_restrim_ctrl = 0x0;

	cfg->com_vco_tune_ctrl = 0x1C;



	cfg->com_svs_mode_clk_sel = 0;

	cfg->com_svs_mode_clk_sel =

			(bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2);

	cfg->com_hsclk_sel = (0x28 | hsclk);

	cfg->com_pll_cctrl_mode0 = cctrl;

	cfg->com_pll_rctrl_mode0 = rctrl;
@@ -757,14 +758,14 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, 
	cfg->com_coreclk_div = HDMI_CORECLK_DIV;



	if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {

		cfg->tx_l0_tx_drv_lvl = 0x39;

		cfg->tx_l0_tx_emp_post1_lvl = 0x33;

		cfg->tx_l1_tx_drv_lvl = 0x39;

		cfg->tx_l1_tx_emp_post1_lvl = 0x33;

		cfg->tx_l2_tx_drv_lvl = 0x39;

		cfg->tx_l2_tx_emp_post1_lvl = 0x33;

		cfg->tx_l3_tx_drv_lvl = 0x39;

		cfg->tx_l3_tx_emp_post1_lvl = 0x30;

		cfg->tx_l0_tx_drv_lvl = 0x25;

		cfg->tx_l0_tx_emp_post1_lvl = 0x23;

		cfg->tx_l1_tx_drv_lvl = 0x25;

		cfg->tx_l1_tx_emp_post1_lvl = 0x23;

		cfg->tx_l2_tx_drv_lvl = 0x25;

		cfg->tx_l2_tx_emp_post1_lvl = 0x23;

		cfg->tx_l3_tx_drv_lvl = 0x22;

		cfg->tx_l3_tx_emp_post1_lvl = 0x27;

		cfg->tx_l0_vmode_ctrl1 = 0x00;

		cfg->tx_l0_vmode_ctrl2 = 0x0D;

		cfg->tx_l1_vmode_ctrl1 = 0x00;
@@ -772,16 +773,17 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, 
		cfg->tx_l2_vmode_ctrl1 = 0x00;

		cfg->tx_l2_vmode_ctrl2 = 0x0D;

		cfg->tx_l3_vmode_ctrl1 = 0x00;

		cfg->tx_l3_vmode_ctrl2 = 0x0D;

	} else {

		cfg->tx_l0_tx_drv_lvl = 0x35;

		cfg->tx_l0_tx_emp_post1_lvl = 0x30;

		cfg->tx_l1_tx_drv_lvl = 0x35;

		cfg->tx_l1_tx_emp_post1_lvl = 0x30;

		cfg->tx_l2_tx_drv_lvl = 0x35;

		cfg->tx_l2_tx_emp_post1_lvl = 0x30;

		cfg->tx_l3_tx_drv_lvl = 0x35;

		cfg->tx_l3_tx_emp_post1_lvl = 0x30;

		cfg->tx_l3_vmode_ctrl2 = 0x00;

		cfg->com_restrim_ctrl = 0x0;

	} else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) {

		cfg->tx_l0_tx_drv_lvl = 0x25;

		cfg->tx_l0_tx_emp_post1_lvl = 0x23;

		cfg->tx_l1_tx_drv_lvl = 0x25;

		cfg->tx_l1_tx_emp_post1_lvl = 0x23;

		cfg->tx_l2_tx_drv_lvl = 0x25;

		cfg->tx_l2_tx_emp_post1_lvl = 0x23;

		cfg->tx_l3_tx_drv_lvl = 0x25;

		cfg->tx_l3_tx_emp_post1_lvl = 0x23;

		cfg->tx_l0_vmode_ctrl1 = 0x00;

		cfg->tx_l0_vmode_ctrl2 = 0x0D;

		cfg->tx_l1_vmode_ctrl1 = 0x00;
@@ -789,7 +791,26 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, 
		cfg->tx_l2_vmode_ctrl1 = 0x00;

		cfg->tx_l2_vmode_ctrl2 = 0x0D;

		cfg->tx_l3_vmode_ctrl1 = 0x00;

		cfg->tx_l3_vmode_ctrl2 = 0x0D;

		cfg->tx_l3_vmode_ctrl2 = 0x00;

		cfg->com_restrim_ctrl = 0x0;

	} else {

		cfg->tx_l0_tx_drv_lvl = 0x20;

		cfg->tx_l0_tx_emp_post1_lvl = 0x20;

		cfg->tx_l1_tx_drv_lvl = 0x20;

		cfg->tx_l1_tx_emp_post1_lvl = 0x20;

		cfg->tx_l2_tx_drv_lvl = 0x20;

		cfg->tx_l2_tx_emp_post1_lvl = 0x20;

		cfg->tx_l3_tx_drv_lvl = 0x20;

		cfg->tx_l3_tx_emp_post1_lvl = 0x20;

		cfg->tx_l0_vmode_ctrl1 = 0x00;

		cfg->tx_l0_vmode_ctrl2 = 0x0E;

		cfg->tx_l1_vmode_ctrl1 = 0x00;

		cfg->tx_l1_vmode_ctrl2 = 0x0E;

		cfg->tx_l2_vmode_ctrl1 = 0x00;

		cfg->tx_l2_vmode_ctrl2 = 0x0E;

		cfg->tx_l3_vmode_ctrl1 = 0x00;

		cfg->tx_l3_vmode_ctrl2 = 0x0E;

		cfg->com_restrim_ctrl = 0xD8;

	}



	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;