Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a49efae authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (56 commits)
  netns: Fix crash by making igmp per namespace
  bnx2x: Version update
  bnx2x: Checkpatch compliance
  bnx2x: Spelling mistakes
  bnx2x: Minor code improvements
  bnx2x: Driver info
  bnx2x: 1G LED does not turn off
  bnx2x: 8073 PHY changes
  bnx2x: Change GPIO for any port
  bnx2x: Pause settings
  bnx2x: Link order with external PHY
  bnx2x: No LRO without Rx checksum
  bnx2x: Wrong structure size
  bnx2x: WoL capability
  bnx2x: Clearing MAC addresses filters
  bnx2x: Delay in while loops
  bnx2x: PBA Table Page Alignment Workaround
  bnx2x: Self-test false positive
  bnx2x: Memory allocation
  bnx2x: HW attention lock
  ...
parents 0ff82850 877acedc

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -3076,6 +3076,7 @@ M: horms@verge.net.au 
P:	Julian Anastasov

M:	ja@ssi.bg

L:	netdev@vger.kernel.org

L:	lvs-devel@vger.kernel.org

S:	Maintained



NFS, SUNRPC, AND LOCKD CLIENTS

drivers/net/bnx2x.h

+52 −35
Original line number Diff line number Diff line
@@ -120,16 +120,8 @@ 
#define SHMEM_RD(bp, field)		REG_RD(bp, SHMEM_ADDR(bp, field))

#define SHMEM_WR(bp, field, val)	REG_WR(bp, SHMEM_ADDR(bp, field), val)



#define NIG_WR(reg, val)	REG_WR(bp, reg, val)

#define EMAC_WR(reg, val)	REG_WR(bp, emac_base + reg, val)

#define BMAC_WR(reg, val)	REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)





#define for_each_queue(bp, var)	for (var = 0; var < bp->num_queues; var++)



#define for_each_nondefault_queue(bp, var) \

				for (var = 1; var < bp->num_queues; var++)

#define is_multi(bp)		(bp->num_queues > 1)

#define EMAC_RD(bp, reg)		REG_RD(bp, emac_base + reg)

#define EMAC_WR(bp, reg, val)		REG_WR(bp, emac_base + reg, val)





/* fast path */
@@ -163,7 +155,7 @@ struct sw_rx_page { 
#define NUM_RX_SGE_PAGES		2

#define RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))

#define MAX_RX_SGE_CNT			(RX_SGE_CNT - 2)

/* RX_SGE_CNT is promissed to be a power of 2 */

/* RX_SGE_CNT is promised to be a power of 2 */

#define RX_SGE_MASK			(RX_SGE_CNT - 1)

#define NUM_RX_SGE			(RX_SGE_CNT * NUM_RX_SGE_PAGES)

#define MAX_RX_SGE			(NUM_RX_SGE - 1)
@@ -258,8 +250,7 @@ struct bnx2x_fastpath { 


	unsigned long		tx_pkt,

				rx_pkt,

				rx_calls,

				rx_alloc_failed;

				rx_calls;

	/* TPA related */

	struct sw_rx_bd		tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];

	u8			tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -275,6 +266,15 @@ struct bnx2x_fastpath { 


#define bnx2x_fp(bp, nr, var)		(bp->fp[nr].var)



#define BNX2X_HAS_TX_WORK(fp) \

			((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \

			 (fp->tx_pkt_prod != fp->tx_pkt_cons))



#define BNX2X_HAS_RX_WORK(fp) \

			(fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb))



#define BNX2X_HAS_WORK(fp)	(BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))





/* MC hsi */

#define MAX_FETCH_BD			13	/* HW max BDs per packet */
@@ -317,7 +317,7 @@ struct bnx2x_fastpath { 
#define RCQ_BD(x)			((x) & MAX_RCQ_BD)





/* This is needed for determening of last_max */

/* This is needed for determining of last_max */

#define SUB_S16(a, b)			(s16)((s16)(a) - (s16)(b))



#define __SGE_MASK_SET_BIT(el, bit) \
@@ -386,20 +386,28 @@ struct bnx2x_fastpath { 
#define TPA_TYPE(cqe_fp_flags)		((cqe_fp_flags) & \

					 (TPA_TYPE_START | TPA_TYPE_END))



#define BNX2X_RX_SUM_OK(cqe) \

			(!(cqe->fast_path_cqe.status_flags & \

			 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \

			  ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))

#define ETH_RX_ERROR_FALGS		ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG



#define BNX2X_IP_CSUM_ERR(cqe) \

			(!((cqe)->fast_path_cqe.status_flags & \

			   ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \

			 ((cqe)->fast_path_cqe.type_error_flags & \

			  ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))



#define BNX2X_L4_CSUM_ERR(cqe) \

			(!((cqe)->fast_path_cqe.status_flags & \

			   ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \

			 ((cqe)->fast_path_cqe.type_error_flags & \

			  ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))



#define BNX2X_RX_CSUM_OK(cqe) \

			(!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))



#define BNX2X_RX_SUM_FIX(cqe) \

			((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \

			  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \

			 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))



#define ETH_RX_ERROR_FALGS	(ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \

				 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \

				 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)





#define FP_USB_FUNC_OFF			(2 + 2*HC_USTORM_SB_NUM_INDICES)

#define FP_CSB_FUNC_OFF			(2 + 2*HC_CSTORM_SB_NUM_INDICES)
@@ -647,6 +655,8 @@ struct bnx2x_eth_stats { 


	u32 brb_drop_hi;

	u32 brb_drop_lo;

	u32 brb_truncate_hi;

	u32 brb_truncate_lo;



	u32 jabber_packets_received;
@@ -663,6 +673,9 @@ struct bnx2x_eth_stats { 
	u32 mac_discard;



	u32 driver_xoff;

	u32 rx_err_discard_pkt;

	u32 rx_skb_alloc_failed;

	u32 hw_csum_err;

};



#define STATS_OFFSET32(stat_name) \
@@ -753,7 +766,6 @@ struct bnx2x { 
	u16			def_att_idx;

	u32			attn_state;

	struct attn_route	attn_group[MAX_DYNAMIC_ATTN_GRPS];

	u32			aeu_mask;

	u32			nig_mask;



	/* slow path ring */
@@ -772,7 +784,7 @@ struct bnx2x { 
	u8			stats_pending;

	u8			set_mac_pending;



	/* End of fileds used in the performance code paths */

	/* End of fields used in the performance code paths */



	int			panic;

	int			msglevel;
@@ -794,9 +806,6 @@ struct bnx2x { 
#define BP_FUNC(bp)			(bp->func)

#define BP_E1HVN(bp)			(bp->func >> 1)

#define BP_L_ID(bp)			(BP_E1HVN(bp) << 2)

/* assorted E1HVN */

#define IS_E1HMF(bp)			(bp->e1hmf != 0)

#define BP_MAX_QUEUES(bp)		(IS_E1HMF(bp) ? 4 : 16)



	int			pm_cap;

	int			pcie_cap;
@@ -821,6 +830,7 @@ struct bnx2x { 
	u32			mf_config;

	u16			e1hov;

	u8			e1hmf;

#define IS_E1HMF(bp)			(bp->e1hmf != 0)



	u8			wol;
@@ -836,7 +846,6 @@ struct bnx2x { 
	u16			rx_ticks_int;

	u16			rx_ticks;



	u32			stats_ticks;

	u32			lin_cnt;



	int			state;
@@ -852,6 +861,7 @@ struct bnx2x { 
#define BNX2X_STATE_ERROR		0xf000



	int			num_queues;

#define BP_MAX_QUEUES(bp)		(IS_E1HMF(bp) ? 4 : 16)



	u32			rx_mode;

#define BNX2X_RX_MODE_NONE		0
@@ -902,10 +912,17 @@ struct bnx2x { 
};





#define for_each_queue(bp, var)	for (var = 0; var < bp->num_queues; var++)



#define for_each_nondefault_queue(bp, var) \

				for (var = 1; var < bp->num_queues; var++)

#define is_multi(bp)		(bp->num_queues > 1)





void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);

void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,

		      u32 len32);

int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);

int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);



static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,

			   int wait)
@@ -976,7 +993,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 
#define PCICFG_LINK_SPEED_SHIFT		16





#define BNX2X_NUM_STATS			39

#define BNX2X_NUM_STATS			42

#define BNX2X_NUM_TESTS			8



#define BNX2X_MAC_LOOPBACK		0
@@ -1007,10 +1024,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 
/* resolution of the rate shaping timer - 100 usec */

#define RS_PERIODIC_TIMEOUT_USEC	100

/* resolution of fairness algorithm in usecs -

   coefficient for clauclating the actuall t fair */

   coefficient for calculating the actual t fair */

#define T_FAIR_COEF			10000000

/* number of bytes in single QM arbitration cycle -

   coeffiecnt for calculating the fairness timer */

   coefficient for calculating the fairness timer */

#define QM_ARB_BYTES			40000

#define FAIR_MEM			2

drivers/net/bnx2x_fw_defs.h

+83 −77
Original line number Diff line number Diff line
@@ -13,15 +13,15 @@ 
#define CSTORM_ASSERT_LIST_OFFSET(idx) \

	(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \

	* 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \

	* 0x4)))

	(IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \

	((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \

	0x40) + (index * 0x4)))

#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \

	* 0x100)) : (0x1900 + (function * 0x40)))

	(IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \

	((function&1) * 0x100)) : (0x1900 + (function * 0x40)))

#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \

	(IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \

	* 0x100)) : (0x1908 + (function * 0x40)))

	(IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \

	((function&1) * 0x100)) : (0x1908 + (function * 0x40)))

#define CSTORM_FUNCTION_MODE_OFFSET \

	(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)

#define CSTORM_HC_BTR_OFFSET(port) \
@@ -50,18 +50,18 @@ 
#define TSTORM_ASSERT_LIST_OFFSET(idx) \

	(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \

	(IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \

	(0x9c8 + (port * 0x2f8) + (client_id * 0x28)))

	(IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \

	: (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))

#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \

	0x4)))

	(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \

	0x28) + (index * 0x4)))

#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1400 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))

#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \

	(IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1408 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))

#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \

	(function * 0x8)))
@@ -79,9 +79,12 @@ 
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \

	(function * 0x38)))

#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \

	(IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \

	0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))

#define TSTORM_RX_PRODS_OFFSET(port, client_id) \

	(IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \

	(0x9c0 + (port * 0x2f8) + (client_id * 0x28)))

	(IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \

	: (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))

#define TSTORM_STATS_FLAGS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \

	(function * 0x8)))
@@ -96,15 +99,15 @@ 
	(IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \

	(0x5450 + (port * 0x1c8) + (clientId * 0x18)))

#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \

	0x4)))

	(IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \

	0x28) + (index * 0x4)))

#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1900 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))

#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \

	(IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1908 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))

#define USTORM_FUNCTION_MODE_OFFSET \

	(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)

#define USTORM_HC_BTR_OFFSET(port) \
@@ -136,15 +139,15 @@ 
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \

	(IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))

#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \

	0x4)))

	(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \

	0x28) + (index * 0x4)))

#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1400 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))

#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \

	(IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \

	* 0xa0)) : (0x1408 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))

#define XSTORM_E1HOV_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)

#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
@@ -157,6 +160,9 @@ 
	(IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)

#define XSTORM_HC_BTR_OFFSET(port) \

	(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))

#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \

	(IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \

	0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))

#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \

	(function * 0x70)))

drivers/net/bnx2x_hsi.h

+8 −8
Original line number Diff line number Diff line
@@ -1268,7 +1268,7 @@ struct doorbell { 




/*

 * IGU driver acknowlegement register

 * IGU driver acknowledgement register

 */

struct igu_ack_register {

#if defined(__BIG_ENDIAN)
@@ -1882,7 +1882,7 @@ struct timers_block_context { 
};



/*

 * structure for easy accessability to assembler

 * structure for easy accessibility to assembler

 */

struct eth_tx_bd_flags {

	u8 as_bitfield;
@@ -2044,7 +2044,7 @@ struct eth_context { 




/*

 * ethernet doorbell

 * Ethernet doorbell

 */

struct eth_tx_doorbell {

#if defined(__BIG_ENDIAN)
@@ -2256,7 +2256,7 @@ struct ramrod_data { 
};



/*

 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)

 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)

 */

union eth_ramrod_data {

	struct ramrod_data general;
@@ -2330,7 +2330,7 @@ struct spe_hdr { 
};



/*

 * ethernet slow path element

 * Ethernet slow path element

 */

union eth_specific_data {

	u8 protocol_data[8];
@@ -2343,7 +2343,7 @@ union eth_specific_data { 
};



/*

 * ethernet slow path element

 * Ethernet slow path element

 */

struct eth_spe {

	struct spe_hdr hdr;
@@ -2615,7 +2615,7 @@ struct tstorm_eth_rx_producers { 




/*

 * common flag to indicate existance of TPA.

 * common flag to indicate existence of TPA.

 */

struct tstorm_eth_tpa_exist {

#if defined(__BIG_ENDIAN)
@@ -2765,7 +2765,7 @@ struct tstorm_common_stats { 
};



/*

 * Eth statistics query sturcture for the eth_stats_quesry ramrod

 * Eth statistics query structure for the eth_stats_query ramrod

 */

struct eth_stats_query {

	struct xstorm_common_stats xstorm_common;

drivers/net/bnx2x_init.h

+13 −13
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, 
/*********************************************************

   There are different blobs for each PRAM section.

   In addition, each blob write operation is divided into a few operations

   in order to decrease the amount of phys. contigious buffer needed.

   in order to decrease the amount of phys. contiguous buffer needed.

   Thus, when we select a blob the address may be with some offset

   from the beginning of PRAM section.

   The same holds for the INT_TABLE sections.
@@ -336,7 +336,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) 
		len = op->str_wr.data_len;

		data = data_base + op->str_wr.data_off;



		/* carefull! it must be in order */

		/* careful! it must be in order */

		if (unlikely(op_type > OP_WB)) {



			/* If E1 only */
@@ -740,7 +740,7 @@ static u8 calc_crc8(u32 data, u8 crc) 
	return crc_res;

}



/* regiesers addresses are not in order

/* registers addresses are not in order

   so these arrays help simplify the code */

static const int cm_start[E1H_FUNC_MAX][9] = {

	{MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,