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Commit 79b4e3cb authored by Alex Matveev's avatar Alex Matveev Committed by Sami Tolvanen
Browse files

FROMLIST: BACKPORT: arm64: make mrs_s and msr_s macros work with LTO 

Clang's integrated assembler does not allow assembly macros defined
in one inline asm block using the .macro directive to be used across
separate asm blocks. LLVM developers consider this a feature and not a
bug, recommending code refactoring:

  https://bugs.llvm.org/show_bug.cgi?id=19749

As binutils doesn't allow macros to be redefined, this change uses
UNDEFINE_MRS_S and UNDEFINE_MSR_S to define corresponding macros
in-place and workaround gcc and clang limitations on redefining macros
across different assembler blocks.

Bug: 62093296
Bug: 67506682
Change-Id: I803fff57f639b0921ef81f90ec4befe802e7eecf
(am from https://patchwork.kernel.org/patch/10060343/

)
Signed-off-by: default avatarAlex Matveev <alxmtvv@gmail.com>
Signed-off-by: default avatarYury Norov <ynorov@caviumnetworks.com>
Signed-off-by: default avatarSami Tolvanen <samitolvanen@google.com>
parent a953df5e

arch/arm64/include/asm/arch_gicv3.h

+54 −12
Original line number Diff line number Diff line
@@ -83,14 +83,20 @@ 
#define read_gicreg(r)							\

	({								\

		u64 reg;						\

		asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg));	\

		asm volatile(DEFINE_MRS_S				\

			"mrs_s %0, " __stringify(r) "\n"		\

			UNDEFINE_MRS_S					\

			: "=r" (reg));					\

		reg;							\

	})



#define write_gicreg(v,r)						\

	do {								\

		u64 __val = (v);					\

		asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\

		asm volatile(DEFINE_MSR_S				\

			"msr_s " __stringify(r) ", %0\n"		\

			UNDEFINE_MSR_S					\

			: : "r" (__val));				\

	} while (0)



/*
@@ -102,13 +108,19 @@ 


static inline void gic_write_eoir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_EOIR1_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)irq));

	isb();

}



static inline void gic_write_dir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_DIR_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)irq));

	isb();

}
@@ -116,7 +128,10 @@ static inline u64 gic_read_iar_common(void) 
{

	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	asm volatile(DEFINE_MRS_S

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n"

		UNDEFINE_MRS_S

		: "=r" (irqstat));

	dsb(sy);

	return irqstat;

}
@@ -135,7 +150,9 @@ static inline u64 gic_read_iar_cavium_thunderx(void) 
	asm volatile(

		"nop;nop;nop;nop\n\t"

		"nop;nop;nop;nop\n\t"

		DEFINE_MRS_S

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"

		UNDEFINE_MRS_S

		"nop;nop;nop;nop"

		: "=r" (irqstat));

	mb();
@@ -145,43 +162,68 @@ static inline u64 gic_read_iar_cavium_thunderx(void) 


static inline void gic_write_pmr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_PMR_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)val));

	/* As per the architecture specification */

	mb();

}



static inline void gic_write_ctlr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_CTLR_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)val));

	isb();

}



static inline void gic_write_grpen1(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_GRPEN1_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)val));

	isb();

}



static inline void gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_SGI1R_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" (val));

	/* As per the architecture specification */

	mb();

}



static inline u32 gic_read_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	asm volatile(DEFINE_MRS_S

		"mrs_s %0, " __stringify(ICC_SRE_EL1) "\n"

		UNDEFINE_MRS_S

		: "=r" (val));

	return val;

}



static inline void gic_write_sre(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_SRE_EL1) ", %0\n"

		UNDEFINE_MSR_S

		: : "r" ((u64)val));

	isb();

}



static inline void gic_write_bpr1(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));

	asm volatile(DEFINE_MSR_S

		"msr_s " __stringify(ICC_BPR1_EL1) ", %x0\n"

		UNDEFINE_MSR_S

		: : "rZ" (val));

}



#define gic_read_typer(c)		readq_relaxed(c)

arch/arm64/include/asm/kvm_hyp.h

+6 −2
Original line number Diff line number Diff line
@@ -29,7 +29,9 @@ 
	({								\

		u64 reg;						\

		asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\

					 "mrs_s %0, " __stringify(r##vh),\

					 DEFINE_MRS_S			\

					 "mrs_s %0, " __stringify(r##vh) "\n"\

					 UNDEFINE_MRS_S,		\

					 ARM64_HAS_VIRT_HOST_EXTN)	\

			     : "=r" (reg));				\

		reg;							\
@@ -39,7 +41,9 @@ 
	do {								\

		u64 __val = (u64)(v);					\

		asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\

					 "msr_s " __stringify(r##vh) ", %x0",\

					 DEFINE_MSR_S			\

					 "msr_s " __stringify(r##vh) ", %x0\n"\

					 UNDEFINE_MSR_S,		\

					 ARM64_HAS_VIRT_HOST_EXTN)	\

					 : : "rZ" (__val));		\

	} while (0)

arch/arm64/include/asm/sysreg.h

+37 −18
Original line number Diff line number Diff line
@@ -243,20 +243,39 @@ 


#include <linux/types.h>



asm(

"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"

"	.equ	.L__reg_num_x\\num, \\num\n"

"	.endr\n"

#define __DEFINE_MRS_MSR_S_REGNUM				\

"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \

"	.equ	.L__reg_num_x\\num, \\num\n"			\

"	.endr\n"						\

"	.equ	.L__reg_num_xzr, 31\n"

"\n"

"	.macro	mrs_s, rt, sreg\n"

"	.inst	0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"



#define DEFINE_MRS_S						\

	__DEFINE_MRS_MSR_S_REGNUM				\

"	.macro	mrs_s, rt, sreg\n"				\

"	.inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"	\

"	.endm\n"

"\n"

"	.macro	msr_s, sreg, rt\n"

"	.inst	0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"



#define DEFINE_MSR_S						\

	__DEFINE_MRS_MSR_S_REGNUM				\

"	.macro	msr_s, sreg, rt\n"				\

"	.inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"		\

"	.endm\n"

);



#define UNDEFINE_MRS_S						\

"	.purgem	mrs_s\n"



#define UNDEFINE_MSR_S						\

"	.purgem	msr_s\n"



#define __mrs_s(r, v)						\

	DEFINE_MRS_S						\

"	mrs_s %0, " __stringify(r) "\n"				\

	UNDEFINE_MRS_S : "=r" (v)



#define __msr_s(r, v)						\

	DEFINE_MSR_S						\

"	msr_s " __stringify(r) ", %x0\n"			\

	UNDEFINE_MSR_S : : "rZ" (v)



/*

 * Unlike read_cpuid, calls to read_sysreg are never expected to be
@@ -284,13 +303,13 @@ asm( 
 */

#define read_sysreg_s(r) ({					\

	u64 __val;						\

	asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val));	\

	asm volatile(__mrs_s(r, __val));			\

	__val;							\

})



#define write_sysreg_s(v, r) do {				\

	u64 __val = (u64)v;						\

	asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val));	\

	u64 __val = (u64)(v);					\

	asm volatile(__msr_s(r, __val));			\

} while (0)



static inline void config_sctlr_el1(u32 clear, u32 set)