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Commit 77f7e22d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gcc-sdm845: Remove the QUP core clocks from under HLOS control" into msm-4.9

parents 603f51d0 bc376fab

drivers/clk/qcom/gcc-sdm845.c

+0 −56
Original line number Diff line number Diff line
@@ -2084,32 +2084,6 @@ static struct clk_branch gcc_qmip_video_ahb_clk = { 
	},

};



static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {

	.halt_reg = 0x17014,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(9),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap0_core_2x_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap0_core_clk = {

	.halt_reg = 0x1700c,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(8),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap0_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap0_s0_clk = {

	.halt_reg = 0x17030,

	.halt_check = BRANCH_HALT_VOTED,
@@ -2254,32 +2228,6 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 
	},

};



static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {

	.halt_reg = 0x18004,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(18),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap1_core_2x_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap1_core_clk = {

	.halt_reg = 0x18008,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(19),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qupv3_wrap1_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qupv3_wrap1_s0_clk = {

	.halt_reg = 0x18014,

	.halt_check = BRANCH_HALT_VOTED,
@@ -3258,8 +3206,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,

	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,

	[GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,

	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,

	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,

	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,

	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,

	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
@@ -3276,8 +3222,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,

	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,

	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,

	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,

	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,

	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,

	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,

	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,

include/dt-bindings/clock/qcom,gcc-sdm845.h

+105 −110
Original line number Diff line number Diff line
@@ -86,116 +86,111 @@ 
#define GCC_QMIP_CAMERA_AHB_CLK					68

#define GCC_QMIP_DISP_AHB_CLK					69

#define GCC_QMIP_VIDEO_AHB_CLK					70

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				71

#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC				72

#define GCC_QUPV3_WRAP0_CORE_CLK				73

#define GCC_QUPV3_WRAP0_S0_CLK					74

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S1_CLK					76

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S2_CLK					78

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S3_CLK					80

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S4_CLK					82

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S5_CLK					84

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S6_CLK					86

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S7_CLK					88

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				89

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				90

#define GCC_QUPV3_WRAP1_CORE_CLK				91

#define GCC_QUPV3_WRAP1_S0_CLK					92

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S1_CLK					94

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S2_CLK					96

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S3_CLK					98

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S4_CLK					100

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S5_CLK					102

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S6_CLK					104

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S7_CLK					106

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				107

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				108

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				109

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				110

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				111

#define GCC_RX1_USB2_CLKREF_CLK					112

#define GCC_RX2_QLINK_CLKREF_CLK				113

#define GCC_RX3_MODEM_CLKREF_CLK				114

#define GCC_SDCC2_AHB_CLK					115

#define GCC_SDCC2_APPS_CLK					116

#define GCC_SDCC2_APPS_CLK_SRC					117

#define GCC_SDCC4_AHB_CLK					118

#define GCC_SDCC4_APPS_CLK					119

#define GCC_SDCC4_APPS_CLK_SRC					120

#define GCC_SYS_NOC_CPUSS_AHB_CLK				121

#define GCC_TSIF_AHB_CLK					122

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				123

#define GCC_TSIF_REF_CLK					124

#define GCC_TSIF_REF_CLK_SRC					125

#define GCC_UFS_CARD_AHB_CLK					126

#define GCC_UFS_CARD_AXI_CLK					127

#define GCC_UFS_CARD_AXI_CLK_SRC				128

#define GCC_UFS_CARD_CLKREF_CLK					129

#define GCC_UFS_CARD_ICE_CORE_CLK				130

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				131

#define GCC_UFS_CARD_PHY_AUX_CLK				132

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				133

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				134

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				135

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				136

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				137

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			138

#define GCC_UFS_MEM_CLKREF_CLK					139

#define GCC_UFS_PHY_AHB_CLK					140

#define GCC_UFS_PHY_AXI_CLK					141

#define GCC_UFS_PHY_AXI_CLK_SRC					142

#define GCC_UFS_PHY_ICE_CORE_CLK				143

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				144

#define GCC_UFS_PHY_PHY_AUX_CLK					145

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				146

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				147

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				148

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				149

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				150

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				151

#define GCC_USB30_PRIM_MASTER_CLK				152

#define GCC_USB30_PRIM_MASTER_CLK_SRC				153

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				154

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			155

#define GCC_USB30_PRIM_SLEEP_CLK				156

#define GCC_USB30_SEC_MASTER_CLK				157

#define GCC_USB30_SEC_MASTER_CLK_SRC				158

#define GCC_USB30_SEC_MOCK_UTMI_CLK				159

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				160

#define GCC_USB30_SEC_SLEEP_CLK					161

#define GCC_USB3_PRIM_CLKREF_CLK				162

#define GCC_USB3_PRIM_PHY_AUX_CLK				163

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				164

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				165

#define GCC_USB3_PRIM_PHY_PIPE_CLK				166

#define GCC_USB3_SEC_CLKREF_CLK					167

#define GCC_USB3_SEC_PHY_AUX_CLK				168

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				169

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				170

#define GCC_USB3_SEC_PHY_PIPE_CLK				171

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				172

#define GCC_VIDEO_AHB_CLK					173

#define GCC_VIDEO_AXI_CLK					174

#define GCC_VIDEO_XO_CLK					175

#define GPLL0							176

#define GPLL0_OUT_EVEN						177

#define GPLL0_OUT_MAIN						178

#define GPLL1							179

#define GPLL1_OUT_MAIN						180

#define GCC_QUPV3_WRAP0_S0_CLK					71

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				72

#define GCC_QUPV3_WRAP0_S1_CLK					73

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				74

#define GCC_QUPV3_WRAP0_S2_CLK					75

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				76

#define GCC_QUPV3_WRAP0_S3_CLK					77

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				78

#define GCC_QUPV3_WRAP0_S4_CLK					79

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				80

#define GCC_QUPV3_WRAP0_S5_CLK					81

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				82

#define GCC_QUPV3_WRAP0_S6_CLK					83

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				84

#define GCC_QUPV3_WRAP0_S7_CLK					85

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				86

#define GCC_QUPV3_WRAP1_S0_CLK					87

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				88

#define GCC_QUPV3_WRAP1_S1_CLK					89

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				90

#define GCC_QUPV3_WRAP1_S2_CLK					91

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				92

#define GCC_QUPV3_WRAP1_S3_CLK					93

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				94

#define GCC_QUPV3_WRAP1_S4_CLK					95

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				96

#define GCC_QUPV3_WRAP1_S5_CLK					97

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				98

#define GCC_QUPV3_WRAP1_S6_CLK					99

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				100

#define GCC_QUPV3_WRAP1_S7_CLK					101

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				102

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				103

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				104

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				105

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				106

#define GCC_RX1_USB2_CLKREF_CLK					107

#define GCC_RX2_QLINK_CLKREF_CLK				108

#define GCC_RX3_MODEM_CLKREF_CLK				109

#define GCC_SDCC2_AHB_CLK					110

#define GCC_SDCC2_APPS_CLK					111

#define GCC_SDCC2_APPS_CLK_SRC					112

#define GCC_SDCC4_AHB_CLK					113

#define GCC_SDCC4_APPS_CLK					114

#define GCC_SDCC4_APPS_CLK_SRC					115

#define GCC_SYS_NOC_CPUSS_AHB_CLK				116

#define GCC_TSIF_AHB_CLK					117

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				118

#define GCC_TSIF_REF_CLK					119

#define GCC_TSIF_REF_CLK_SRC					120

#define GCC_UFS_CARD_AHB_CLK					121

#define GCC_UFS_CARD_AXI_CLK					122

#define GCC_UFS_CARD_AXI_CLK_SRC				123

#define GCC_UFS_CARD_CLKREF_CLK					124

#define GCC_UFS_CARD_ICE_CORE_CLK				125

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				126

#define GCC_UFS_CARD_PHY_AUX_CLK				127

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				128

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				129

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				130

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				131

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				132

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			133

#define GCC_UFS_MEM_CLKREF_CLK					134

#define GCC_UFS_PHY_AHB_CLK					135

#define GCC_UFS_PHY_AXI_CLK					136

#define GCC_UFS_PHY_AXI_CLK_SRC					137

#define GCC_UFS_PHY_ICE_CORE_CLK				138

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				139

#define GCC_UFS_PHY_PHY_AUX_CLK					140

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				141

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				142

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				143

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				144

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				145

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				146

#define GCC_USB30_PRIM_MASTER_CLK				147

#define GCC_USB30_PRIM_MASTER_CLK_SRC				148

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				149

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			150

#define GCC_USB30_PRIM_SLEEP_CLK				151

#define GCC_USB30_SEC_MASTER_CLK				152

#define GCC_USB30_SEC_MASTER_CLK_SRC				153

#define GCC_USB30_SEC_MOCK_UTMI_CLK				154

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				155

#define GCC_USB30_SEC_SLEEP_CLK					156

#define GCC_USB3_PRIM_CLKREF_CLK				157

#define GCC_USB3_PRIM_PHY_AUX_CLK				158

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				159

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				160

#define GCC_USB3_PRIM_PHY_PIPE_CLK				161

#define GCC_USB3_SEC_CLKREF_CLK					162

#define GCC_USB3_SEC_PHY_AUX_CLK				163

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				164

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				165

#define GCC_USB3_SEC_PHY_PIPE_CLK				166

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				167

#define GCC_VIDEO_AHB_CLK					168

#define GCC_VIDEO_AXI_CLK					169

#define GCC_VIDEO_XO_CLK					170

#define GPLL0							171

#define GPLL0_OUT_EVEN						172

#define GPLL0_OUT_MAIN						173

#define GPLL1							174

#define GPLL1_OUT_MAIN						175



/* GCC reset clocks */

#define GCC_GPU_BCR						0