Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h +1 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ static struct cam_ife_csid_ipp_reg_offset cam_ife_csid_170_ipp_reg_offset = { .csid_ipp_timestamp_perv1_eof_addr = 0x2ac, /* configurations */ .pix_store_en_shift_val = 7, .early_eof_en_shift_val = 29, }; static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_0_reg_offset = { Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +10 −0 Original line number Diff line number Diff line Loading @@ -1419,6 +1419,16 @@ static int cam_ife_csid_init_config_ipp_path( csid_reg->ipp_reg->csid_ipp_vcrop_addr); CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", csid_hw->hw_intf->hw_idx, val); /* Enable generating early eof strobe based on crop config */ if (!(csid_hw->csid_debug & CSID_DEBUG_DISABLE_EARLY_EOF)) { val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_ipp_cfg0_addr); val |= (1 << csid_reg->ipp_reg->early_eof_en_shift_val); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_ipp_cfg0_addr); } } /* set frame drop pattern to 0 and period to 1 */ Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +2 −1 Original line number Diff line number Diff line Loading @@ -77,7 +77,7 @@ #define CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5) #define CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) #define CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) #define CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) /* enum cam_csid_path_halt_mode select the path halt mode control */ enum cam_csid_path_halt_mode { Loading Loading @@ -137,6 +137,7 @@ struct cam_ife_csid_ipp_reg_offset { /* configuration */ uint32_t pix_store_en_shift_val; uint32_t early_eof_en_shift_val; }; struct cam_ife_csid_rdi_reg_offset { Loading Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h +1 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ static struct cam_ife_csid_ipp_reg_offset cam_ife_csid_170_ipp_reg_offset = { .csid_ipp_timestamp_perv1_eof_addr = 0x2ac, /* configurations */ .pix_store_en_shift_val = 7, .early_eof_en_shift_val = 29, }; static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_0_reg_offset = { Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +10 −0 Original line number Diff line number Diff line Loading @@ -1419,6 +1419,16 @@ static int cam_ife_csid_init_config_ipp_path( csid_reg->ipp_reg->csid_ipp_vcrop_addr); CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", csid_hw->hw_intf->hw_idx, val); /* Enable generating early eof strobe based on crop config */ if (!(csid_hw->csid_debug & CSID_DEBUG_DISABLE_EARLY_EOF)) { val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_ipp_cfg0_addr); val |= (1 << csid_reg->ipp_reg->early_eof_en_shift_val); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_ipp_cfg0_addr); } } /* set frame drop pattern to 0 and period to 1 */ Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +2 −1 Original line number Diff line number Diff line Loading @@ -77,7 +77,7 @@ #define CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5) #define CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) #define CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) #define CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) /* enum cam_csid_path_halt_mode select the path halt mode control */ enum cam_csid_path_halt_mode { Loading Loading @@ -137,6 +137,7 @@ struct cam_ife_csid_ipp_reg_offset { /* configuration */ uint32_t pix_store_en_shift_val; uint32_t early_eof_en_shift_val; }; struct cam_ife_csid_rdi_reg_offset { Loading