Commit 76bc0987 authored Jun 20, 2017 by Steve Cohen Committed by Gerrit - the friendly Code Review server Jul 25, 2017

ARM: dts: msm: Add missing clock-ctrl setting for write-back on sdm845



SDE DRM driver reads this value for WB2 clock gating control. If not
present in device node, the current driver writes to a read-only
register (offset 0.0 from SSPP_TOP0). This patch fixes the bug.

CRs-Fixed: 2072416
Change-Id: I9d181fe9cf1b8b9955ef160924f1ca1f1b7e9efe
Signed-off-by: Steve Cohen <cohens@codeaurora.org>

parent 814e5c69

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+2 −1

Original line number	Diff line number	Diff line
		@@ -65,9 +65,10 @@

		qcom,sde-wb-off = <0x66000>;
		qcom,sde-wb-size = <0x2c8>;

		qcom,sde-wb-xin-id = <6>;
		qcom,sde-wb-id = <2>;
		qcom,sde-wb-clk-ctrl = <0x3b8 24>;

		qcom,sde-intf-off = <0x6b000 0x6b800
		0x6c000 0x6c800>;
		qcom,sde-intf-size = <0x280>;