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Commit 76bad29b authored by Soundrapandian Jeyaprakash's avatar Soundrapandian Jeyaprakash Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Remove the csid clocks in phy for sdm845" into dev/msm-4.9-camx

parents 1184547c b1638752

arch/arm64/boot/dts/qcom/sdm845-camera.dtsi

+9 −21
Original line number Diff line number Diff line
@@ -36,9 +36,7 @@ 
			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY0_CLK>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,

			<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,

			<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>;

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",
@@ -46,12 +44,10 @@ 
			"cphy_rx_clk_src",

			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk",

			"ife_0_csid_clk",

			"ife_0_csid_clk_src";

			"csi0phytimer_clk";

		clock-cntl-level = "turbo";

		clock-rates =

			<0 0 0 0 320000000 0 269333333 0 0 384000000>;

			<0 0 0 0 320000000 0 269333333 0>;

		status = "ok";

	};
@@ -74,9 +70,7 @@ 
			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY1_CLK>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,

			<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,

			<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>;

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",
@@ -84,12 +78,10 @@ 
			"cphy_rx_clk_src",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk",

			"ife_1_csid_clk",

			"ife_1_csid_clk_src";

			"csi1phytimer_clk";

		clock-cntl-level = "turbo";

		clock-rates =

			<0 0 0 0 320000000 0 269333333 0 0 384000000>;

			<0 0 0 0 320000000 0 269333333 0>;



		status = "ok";

	};
@@ -113,9 +105,7 @@ 
			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY2_CLK>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,

			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,

			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>;

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "camnoc_axi_clk",

			"soc_ahb_clk",

			"slow_ahb_src_clk",
@@ -123,12 +113,10 @@ 
			"cphy_rx_clk_src",

			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk",

			"ife_lite_csid_clk",

			"ife_lite_csid_clk_src";

			"csi2phytimer_clk";

		clock-cntl-level = "turbo";

		clock-rates =

			<0 0 0 0 320000000 0 269333333 0 0 384000000>;

			<0 0 0 0 320000000 0 269333333 0>;

		status = "ok";

	};