Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7682f9e8 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: uasm: Add SLT uasm instruction 



It will be used later on by bpf-jit

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/7120/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9d987369

arch/mips/include/asm/uasm.h

+1 −0
Original line number Diff line number Diff line
@@ -150,6 +150,7 @@ Ip_u2s3u1(_scd); 
Ip_u2s3u1(_sd);

Ip_u2u1u3(_sll);

Ip_u3u2u1(_sllv);

Ip_s3s1s2(_slt);

Ip_u2u1s3(_sltiu);

Ip_u3u1u2(_sltu);

Ip_u2u1u3(_sra);

arch/mips/include/uapi/asm/inst.h

+1 −0
Original line number Diff line number Diff line
@@ -273,6 +273,7 @@ enum mm_32a_minor_op { 
	mm_and_op = 0x250,

	mm_or32_op = 0x290,

	mm_xor32_op = 0x310,

	mm_slt_op = 0x350,

	mm_sltu_op = 0x390,

};

arch/mips/mm/uasm-micromips.c

+1 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ static struct insn insn_table_MM[] = { 
	{ insn_sd, 0, 0 },

	{ insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },

	{ insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },

	{ insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },

	{ insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },

	{ insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },

	{ insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },

arch/mips/mm/uasm-mips.c

+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ static struct insn insn_table[] = { 
	{ insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

	{ insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },

	{ insn_sllv,  M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD },

	{ insn_slt,  M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD },

	{ insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },

	{ insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },

	{ insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },

arch/mips/mm/uasm.c

+2 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ enum opcode { 
	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,

	insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,

	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,

	insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra,

	insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,

	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,

	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,

	insn_xor, insn_xori, insn_yield,
@@ -296,6 +296,7 @@ I_u2s3u1(_scd) 
I_u2s3u1(_sd)

I_u2u1u3(_sll)

I_u3u2u1(_sllv)

I_s3s1s2(_slt)

I_u2u1s3(_sltiu)

I_u3u1u2(_sltu)

I_u2u1u3(_sra)