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Commit 75c3207b authored by Channagoud Kadabi's avatar Channagoud Kadabi
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ARM: dts: msm: Update CPUID for msmskunk



MPIDR for msmskunk cores has CPUID moved to bit 8. Update the reg
property of CPU node to match the MPIDR values, the new cpuid for
core 0..7 are 0x0..0x700.

CRs-Fixed: 1055760
Change-Id: I2b981c56d3dca3198de27229162f50c7915f72b0
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
parent 79d72f79
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+7 −7
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@
		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -68,7 +68,7 @@
		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -84,7 +84,7 @@
		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -100,7 +100,7 @@
		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			reg = <0x0 0x400>;
			enable-method = "spin-table";
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -116,7 +116,7 @@
		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x101>;
			reg = <0x0 0x500>;
			enable-method = "spin-table";
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -132,7 +132,7 @@
		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x102>;
			reg = <0x0 0x600>;
			enable-method = "spin-table";
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
@@ -148,7 +148,7 @@
		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x103>;
			reg = <0x0 0x700>;
			enable-method = "spin-table";
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;