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Commit 759a45c6 authored by Siva Kumar Akkireddi's avatar Siva Kumar Akkireddi
Browse files

msm: ep_pcie: Enable update of pcie device and vendor id 



Add code to enable update of pcie device id and vendor id as some devices
need it to enumerate correctly when connected to the host.

Signed-off-by: default avatarSiva Kumar Akkireddi <sivaa@codeaurora.org>
Change-Id: I8493aef8c5b741d578735c717d77bf5c18c65ea4
parent a212cf53

Documentation/devicetree/bindings/pci/msm_ep_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -49,6 +49,8 @@ Optional Properties: 
  - qcom,phy-status-reg: Register offset for PHY status.

  - qcom,dbi-base-reg: Register offset for DBI base address.

  - qcom,slv-space-reg: Register offset for slave address space size.

  - qcom,pcie-vendor-id: Vendor id to be written to the Vendor ID register.

  - qcom,pcie-device-id: Device id to be written to the Device ID register.

  - qcom,pcie-link-speed: generation of PCIe link speed. The value could be

    1, 2 or 3.

  - qcom,pcie-active-config: boolean type; active configuration of PCIe

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+4 −0
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ 
#define PCIE20_ELBI_CS2_ENABLE         0xA4



#define PCIE20_DEVICE_ID_VENDOR_ID     0x00

#define PCIE20_MASK_DEVICE_ID          GENMASK(31, 16)

#define PCIE20_MASK_VENDOR_ID          GENMASK(15, 0)

#define PCIE20_COMMAND_STATUS          0x04

#define PCIE20_CLASS_CODE_REVISION_ID  0x08

#define PCIE20_BIST_HDR_TYPE           0x0C
@@ -326,6 +328,8 @@ struct ep_pcie_dev_t { 


	struct msm_bus_scale_pdata   *bus_scale_table;

	u32                          bus_client;

	u16                          vendor_id;

	u16                          device_id;

	u32                          link_speed;

	bool                         active_config;

	bool                         aggregated_irq;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+35 −0
Original line number Diff line number Diff line
@@ -673,6 +673,17 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
		ep_pcie_write_mask(dev->dm_core + PCIE20_MISC_CONTROL_1, 0,

			BIT(0));



		/* Set Vendor ID and Device ID */

		if (ep_pcie_dev.device_id != 0xFFFF)

			ep_pcie_write_reg_field(dev->dm_core,

						PCIE20_DEVICE_ID_VENDOR_ID,

						PCIE20_MASK_DEVICE_ID,

						ep_pcie_dev.device_id);

		if (ep_pcie_dev.vendor_id != 0xFFFF)

			ep_pcie_write_reg_field(dev->dm_core,

						PCIE20_DEVICE_ID_VENDOR_ID,

						PCIE20_MASK_VENDOR_ID,

						ep_pcie_dev.vendor_id);

		/* Set class code and revision ID */

		ep_pcie_write_reg(dev->dm_core, PCIE20_CLASS_CODE_REVISION_ID,

			0xff000000);
@@ -2518,6 +2529,30 @@ static int ep_pcie_probe(struct platform_device *pdev) 
		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: pcie-link-speed:%d.\n",

			ep_pcie_dev.rev, ep_pcie_dev.link_speed);



	ep_pcie_dev.vendor_id = 0xFFFF;

	ret = of_property_read_u16((&pdev->dev)->of_node,

				"qcom,pcie-vendor-id",

				&ep_pcie_dev.vendor_id);

	if (ret)

		EP_PCIE_DBG(&ep_pcie_dev,

				"PCIe V%d: pcie-vendor-id does not exist.\n",

				ep_pcie_dev.rev);

	else

		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: pcie-vendor-id:%d.\n",

				ep_pcie_dev.rev, ep_pcie_dev.vendor_id);



	ep_pcie_dev.device_id = 0xFFFF;

	ret = of_property_read_u16((&pdev->dev)->of_node,

				"qcom,pcie-device-id",

				&ep_pcie_dev.device_id);

	if (ret)

		EP_PCIE_DBG(&ep_pcie_dev,

				"PCIe V%d: pcie-device-id does not exist.\n",

				ep_pcie_dev.rev);

	else

		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: pcie-device-id:%d.\n",

				ep_pcie_dev.rev, ep_pcie_dev.device_id);



	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,dbi-base-reg",

				&ep_pcie_dev.dbi_base_reg);