Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7574e57e authored by Yuanfang Zhang's avatar Yuanfang Zhang
Browse files

ARM: dts: msm: Add qcom,cti-save property for MSM8953 



Direct accessing to the CPU-CTI register causes the device
to breakdown when the cpu enters a low power mode,it is necessary
to verify whether the cpu enter low power mode. This function of
cti_cpu_verify_access is used for verification, this function
 work normally depend on "qcom,cti-save",so add this property.

Change-Id: Ibb24ddf750013fe3fa2c2cce6e4bd2d68548ae58
Signed-off-by: default avatarYuanfang Zhang <zhangyuanfang@codeaurora.org>
parent 94aaaf65

arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi

+8 −0
Original line number Original line Diff line number Diff line
@@ -890,6 +890,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";

		coresight-name = "coresight-cti-cpu0";

		cpu = <&CPU0>;

		cpu = <&CPU0>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -904,6 +905,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu1";

		coresight-name = "coresight-cti-cpu1";

		cpu = <&CPU1>;

		cpu = <&CPU1>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -918,6 +920,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu2";

		coresight-name = "coresight-cti-cpu2";

		cpu = <&CPU2>;

		cpu = <&CPU2>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -932,6 +935,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu3";

		coresight-name = "coresight-cti-cpu3";

		cpu = <&CPU3>;

		cpu = <&CPU3>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -946,6 +950,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";

		coresight-name = "coresight-cti-cpu4";

		cpu = <&CPU4>;

		cpu = <&CPU4>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -960,6 +965,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";

		coresight-name = "coresight-cti-cpu5";

		cpu = <&CPU5>;

		cpu = <&CPU5>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -974,6 +980,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";

		coresight-name = "coresight-cti-cpu6";

		cpu = <&CPU6>;

		cpu = <&CPU6>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -988,6 +995,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";

		coresight-name = "coresight-cti-cpu7";

		cpu = <&CPU7>;

		cpu = <&CPU7>;

		qcom,cit-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;

arch/arm64/boot/dts/qcom/sdm632-coresight.dtsi

+4 −1
Original line number Original line Diff line number Diff line
@@ -104,6 +104,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";

		coresight-name = "coresight-cti-cpu4";

		cpu = <&CPU4>;

		cpu = <&CPU4>;

		qcom,cti-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -118,7 +119,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";

		coresight-name = "coresight-cti-cpu5";

		cpu = <&CPU5>;

		cpu = <&CPU5>;



		qcom,cti-save;

		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "apb_pclk";

		clock-names = "apb_pclk";
@@ -132,6 +133,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";

		coresight-name = "coresight-cti-cpu6";

		cpu = <&CPU6>;

		cpu = <&CPU6>;

		qcom,cti-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -146,6 +148,7 @@ 
		reg-names = "cti-base";

		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";

		coresight-name = "coresight-cti-cpu7";

		cpu = <&CPU7>;

		cpu = <&CPU7>;

		qcom,cti-save;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;