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Commit 7527d44b authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Disallow L2PC during wake up from SLUMBER"

parents dc3be0de c169c32e

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −0
Original line number Diff line number Diff line
@@ -143,6 +143,9 @@ Optional Properties: 
				rendering thread is running on masked CPUs.

				Bit 0 is for CPU-0, bit 1 is for CPU-1...



- qcom,l2pc-update-queue:

				Disables L2PC on masked CPUs at queue time when it's true.



- qcom,snapshot-size:

				Specify the size of snapshot in bytes. This will override

				snapshot size defined in the driver code.

drivers/gpu/msm/adreno.c

+4 −0
Original line number Diff line number Diff line
@@ -1451,6 +1451,10 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	/* make sure ADRENO_DEVICE_STARTED is not set here */

	BUG_ON(test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv));



	/* disallow l2pc during wake up to improve GPU wake up time */

	kgsl_pwrctrl_update_l2pc(&adreno_dev->dev,

			KGSL_L2PC_WAKEUP_TIMEOUT);



	pm_qos_update_request(&device->pwrctrl.pm_qos_req_dma,

			pmqos_wakeup_vote);

drivers/gpu/msm/adreno_dispatch.c

+3 −1
Original line number Diff line number Diff line
@@ -1464,7 +1464,9 @@ int adreno_dispatcher_queue_cmds(struct kgsl_device_private *dev_priv, 


	spin_unlock(&drawctxt->lock);



	kgsl_pwrctrl_update_l2pc(&adreno_dev->dev);

	if (device->pwrctrl.l2pc_update_queue)

		kgsl_pwrctrl_update_l2pc(&adreno_dev->dev,

				KGSL_L2PC_QUEUE_TIMEOUT);



	/* Add the context to the dispatcher pending list */

	dispatcher_queue_context(adreno_dev, drawctxt);

drivers/gpu/msm/kgsl_pwrctrl.c

+8 −9
Original line number Diff line number Diff line
@@ -44,13 +44,6 @@ 


#define DEFAULT_BUS_P 25



/*

 * The effective duration of qos request in usecs. After

 * timeout, qos request is cancelled automatically.

 * Kept 80ms default, inline with default GPU idle time.

 */

#define KGSL_L2PC_CPU_TIMEOUT	(80 * 1000)



/* Order deeply matters here because reasons. New entries go on the end */

static const char * const clocks[] = {

	"src_clk",
@@ -544,12 +537,14 @@ EXPORT_SYMBOL(kgsl_pwrctrl_set_constraint); 
/**

 * kgsl_pwrctrl_update_l2pc() - Update existing qos request

 * @device: Pointer to the kgsl_device struct

 * @timeout_us: the effective duration of qos request in usecs.

 *

 * Updates an existing qos request to avoid L2PC on the

 * CPUs (which are selected through dtsi) on which GPU

 * thread is running. This would help for performance.

 */

void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device)

void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device,

			unsigned long timeout_us)

{

	int cpu;
@@ -563,7 +558,7 @@ void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device) 
		pm_qos_update_request_timeout(

				&device->pwrctrl.l2pc_cpus_qos,

				device->pwrctrl.pm_qos_cpu_mask_latency,

				KGSL_L2PC_CPU_TIMEOUT);

				timeout_us);

	}

}

EXPORT_SYMBOL(kgsl_pwrctrl_update_l2pc);
@@ -2194,6 +2189,10 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
	kgsl_property_read_u32(device, "qcom,l2pc-cpu-mask",

			&pwr->l2pc_cpus_mask);



	pwr->l2pc_update_queue = of_property_read_bool(

				device->pdev->dev.of_node,

				"qcom,l2pc-update-queue");



	pm_runtime_enable(&pdev->dev);



	ocmem_bus_node = of_find_node_by_name(

drivers/gpu/msm/kgsl_pwrctrl.h

+17 −1
Original line number Diff line number Diff line
@@ -50,6 +50,19 @@ 
#define KGSL_PWR_DEL_LIMIT 1

#define KGSL_PWR_SET_LIMIT 2



/*

 * The effective duration of qos request in usecs at queue time.

 * After timeout, qos request is cancelled automatically.

 * Kept 80ms default, inline with default GPU idle time.

 */

#define KGSL_L2PC_QUEUE_TIMEOUT	(80 * 1000)



/*

 * The effective duration of qos request in usecs at wakeup time.

 * After timeout, qos request is cancelled automatically.

 */

#define KGSL_L2PC_WAKEUP_TIMEOUT (10 * 1000)



enum kgsl_pwrctrl_timer_type {

	KGSL_PWR_IDLE_TIMER,

};
@@ -127,6 +140,7 @@ struct kgsl_regulator { 
 * @irq_name - resource name for the IRQ

 * @clk_stats - structure of clock statistics

 * @l2pc_cpus_mask - mask to avoid L2PC on masked CPUs

 * @l2pc_update_queue - Boolean flag to avoid L2PC on masked CPUs at queue time

 * @l2pc_cpus_qos - qos structure to avoid L2PC on CPUs

 * @pm_qos_req_dma - the power management quality of service structure

 * @pm_qos_active_latency - allowed CPU latency in microseconds when active
@@ -180,6 +194,7 @@ struct kgsl_pwrctrl { 
	const char *irq_name;

	struct kgsl_clk_stats clk_stats;

	unsigned int l2pc_cpus_mask;

	bool l2pc_update_queue;

	struct pm_qos_request l2pc_cpus_qos;

	struct pm_qos_request pm_qos_req_dma;

	unsigned int pm_qos_active_latency;
@@ -244,5 +259,6 @@ int kgsl_active_count_wait(struct kgsl_device *device, int count); 
void kgsl_pwrctrl_busy_time(struct kgsl_device *device, u64 time, u64 busy);

void kgsl_pwrctrl_set_constraint(struct kgsl_device *device,

			struct kgsl_pwr_constraint *pwrc, uint32_t id);

void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device);

void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device,

			unsigned long timeout_us);

#endif /* __KGSL_PWRCTRL_H */