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Commit 73fed0ef authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Jani Nikula
Browse files

drm/i915/gen9: fix the watermark res_blocks value 



We forgot the "res_blocks += y_tile_minimum" that's described on step
V of our documentation.

Again, this should only affect the Y tiling cases.

It looks like the relevant code was introduced in 0fda6568, but
there's always the possibility that it matched our specification when
it was introduced, and then the specification changed while the code
stayed the same. So we can't really say this was a regression, but
let's try to add a "Fixes" tag anyway to help backporting.

v2: Try to add a "Fixes" tag (Maarten).

Fixes: 0fda6568 ("drm/i915/skl: Update watermarks for Y tiling")
Cc: stable@vger.kernel.org
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarLyude <cpaul@redhat.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1474578035-424-8-git-send-email-paulo.r.zanoni@intel.com


(cherry picked from commit 75676ed423a6acf9e2b1df52fbc036a51e11fb7a)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent cf6c525a

drivers/gpu/drm/i915/intel_pm.c

+7 −5
Original line number Original line Diff line number Diff line
@@ -3552,7 +3552,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
	uint8_t cpp;

	uint8_t cpp;

	uint32_t width = 0, height = 0;

	uint32_t width = 0, height = 0;

	uint32_t plane_pixel_rate;

	uint32_t plane_pixel_rate;

	uint32_t y_min_scanlines;

	uint32_t y_tile_minimum, y_min_scanlines;





	if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {

	if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {

		*enabled = false;

		*enabled = false;
@@ -3609,10 +3609,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
				 latency,

				 latency,

				 plane_blocks_per_line);

				 plane_blocks_per_line);





	y_tile_minimum = plane_blocks_per_line * y_min_scanlines;



	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||

	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||

	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {

	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {

		uint32_t y_tile_minimum = plane_blocks_per_line *

					  y_min_scanlines;

		selected_result = max(method2, y_tile_minimum);

		selected_result = max(method2, y_tile_minimum);

	} else {

	} else {

		if ((ddb_allocation / plane_blocks_per_line) >= 1)

		if ((ddb_allocation / plane_blocks_per_line) >= 1)
@@ -3626,11 +3626,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 




	if (level >= 1 && level <= 7) {

	if (level >= 1 && level <= 7) {

		if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||

		if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||

		    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)

		    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {

			res_blocks += y_tile_minimum;

			res_lines += y_min_scanlines;

			res_lines += y_min_scanlines;

		else

		} else {

			res_blocks++;

			res_blocks++;

		}

		}

	}





	if (res_blocks >= ddb_allocation || res_lines > 31) {

	if (res_blocks >= ddb_allocation || res_lines > 31) {

		*enabled = false;

		*enabled = false;