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Commit 73c0d752 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'stable' of... 

Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile into akpm

Pull tile bugfixes from Chris Metcalf:
 "This includes a variety of minor bug fixes, mostly to do with testing
  "make allyesconfig", "make allmodconfig", "make allnoconfig", inspired
  to Tejun Heo's observation about Kconfig.freezer not being included.

  The largest changes are just syntax changes removing the tile-specific
  use of a macro named INT_MASK, which is way too commonly redefined
  throughout driver code"

* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  tile: tag some code with #ifdef CONFIG_COMPAT
  tile: fix memcpy_*io functions for allnoconfig
  tile: export a handful of symbols appropriately
  drm: fix compile failure by including <linux/swiotlb.h>
  tile: avoid defining INT_MASK macro in <arch/interrupts.h>
  tile: provide "screen_info" when enabling VT
  drivers/input/joystick/analog.c: enable precise timer
  tile: include kernel/Kconfig.freezer in tile Kconfig
  tile: remove an unused variable in copy_thread()
parents 983ca836 570fd501

arch/tile/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ config ARCH_DEFCONFIG 


source "init/Kconfig"



source "kernel/Kconfig.freezer"



menu "Tilera-specific configuration"



config NR_CPUS

arch/tile/include/asm/io.h

+5 −1
Original line number Diff line number Diff line
@@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr) 
#define iowrite32 writel

#define iowrite64 writeq



static inline void memset_io(void *dst, int val, size_t len)

#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)



static inline void memset_io(volatile void *dst, int val, size_t len)

{

	int x;

	BUG_ON((unsigned long)dst & 0x3);
@@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, 
		writel(*(u32 *)(src + x), dst + x);

}



#endif



/*

 * The Tile architecture does not support IOPORT, even with PCI.

 * Unfortunately we can't yet simply not declare these methods,

arch/tile/include/asm/irqflags.h

+10 −22
Original line number Diff line number Diff line
@@ -18,32 +18,20 @@ 
#include <arch/interrupts.h>

#include <arch/chip.h>



#if !defined(__tilegx__) && defined(__ASSEMBLY__)



/*

 * The set of interrupts we want to allow when interrupts are nominally

 * disabled.  The remainder are effectively "NMI" interrupts from

 * the point of view of the generic Linux code.  Note that synchronous

 * interrupts (aka "non-queued") are not blocked by the mask in any case.

 */

#if CHIP_HAS_AUX_PERF_COUNTERS()

#define LINUX_MASKABLE_INTERRUPTS_HI \

	(~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))

#else

#define LINUX_MASKABLE_INTERRUPTS_HI \

	(~(INT_MASK_HI(INT_PERF_COUNT)))

#endif



#else



#if CHIP_HAS_AUX_PERF_COUNTERS()

#define LINUX_MASKABLE_INTERRUPTS \

	(~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))

#else

#define LINUX_MASKABLE_INTERRUPTS \

	(~(INT_MASK(INT_PERF_COUNT)))

#endif

	(~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))



#if CHIP_HAS_SPLIT_INTR_MASK()

/* The same macro, but for the two 32-bit SPRs separately. */

#define LINUX_MASKABLE_INTERRUPTS_LO (-1)

#define LINUX_MASKABLE_INTERRUPTS_HI \

	(~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))

#endif



#ifndef __ASSEMBLY__
@@ -126,7 +114,7 @@ 
 * to know our current state.

 */

DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);

#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)

#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)



/* Disable interrupts. */

#define arch_local_irq_disable() \
@@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 


/* Prevent the given interrupt from being enabled next time we enable irqs. */

#define arch_local_irq_mask(interrupt) \

	(__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))

	(__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))



/* Prevent the given interrupt from being enabled immediately. */

#define arch_local_irq_mask_now(interrupt) do { \
@@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 


/* Allow the given interrupt to be enabled next time we enable irqs. */

#define arch_local_irq_unmask(interrupt) \

	(__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))

	(__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))



/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */

#define arch_local_irq_unmask_now(interrupt) do { \
@@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 
/* Disable interrupts. */

#define IRQ_DISABLE(tmp0, tmp1)					\

	{							\

	 movei  tmp0, -1;					\

	 movei  tmp0, LINUX_MASKABLE_INTERRUPTS_LO;		\

	 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI)	\

	};							\

	{							\

arch/tile/include/uapi/arch/interrupts_32.h

+198 −196
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#ifndef __ARCH_INTERRUPTS_H__

#define __ARCH_INTERRUPTS_H__



#ifndef __KERNEL__

/** Mask for an interrupt. */

/* Note: must handle breaking interrupts into high and low words manually. */

#define INT_MASK_LO(intno) (1 << (intno))
@@ -23,6 +24,7 @@ 
#ifndef __ASSEMBLER__

#define INT_MASK(intno) (1ULL << (intno))

#endif

#endif





/** Where a given interrupt executes */
@@ -92,216 +94,216 @@ 


#ifndef __ASSEMBLER__

#define QUEUED_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_DMATLB_MISS) | \

    INT_MASK(INT_DMATLB_ACCESS) | \

    INT_MASK(INT_SNITLB_MISS) | \

    INT_MASK(INT_SN_NOTIFY) | \

    INT_MASK(INT_SN_FIREWALL) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_DMA_NOTIFY) | \

    INT_MASK(INT_IDN_CA) | \

    INT_MASK(INT_UDN_CA) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DMA_ASID) | \

    INT_MASK(INT_SNI_ASID) | \

    INT_MASK(INT_DMA_CPL) | \

    INT_MASK(INT_SN_CPL) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    (1ULL << INT_MEM_ERROR) | \

    (1ULL << INT_DMATLB_MISS) | \

    (1ULL << INT_DMATLB_ACCESS) | \

    (1ULL << INT_SNITLB_MISS) | \

    (1ULL << INT_SN_NOTIFY) | \

    (1ULL << INT_SN_FIREWALL) | \

    (1ULL << INT_IDN_FIREWALL) | \

    (1ULL << INT_UDN_FIREWALL) | \

    (1ULL << INT_TILE_TIMER) | \

    (1ULL << INT_IDN_TIMER) | \

    (1ULL << INT_UDN_TIMER) | \

    (1ULL << INT_DMA_NOTIFY) | \

    (1ULL << INT_IDN_CA) | \

    (1ULL << INT_UDN_CA) | \

    (1ULL << INT_IDN_AVAIL) | \

    (1ULL << INT_UDN_AVAIL) | \

    (1ULL << INT_PERF_COUNT) | \

    (1ULL << INT_INTCTRL_3) | \

    (1ULL << INT_INTCTRL_2) | \

    (1ULL << INT_INTCTRL_1) | \

    (1ULL << INT_INTCTRL_0) | \

    (1ULL << INT_BOOT_ACCESS) | \

    (1ULL << INT_WORLD_ACCESS) | \

    (1ULL << INT_I_ASID) | \

    (1ULL << INT_D_ASID) | \

    (1ULL << INT_DMA_ASID) | \

    (1ULL << INT_SNI_ASID) | \

    (1ULL << INT_DMA_CPL) | \

    (1ULL << INT_SN_CPL) | \

    (1ULL << INT_DOUBLE_FAULT) | \

    (1ULL << INT_AUX_PERF_COUNT) | \

    0)

#define NONQUEUED_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_SN_ACCESS) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_IDN_REFILL) | \

    INT_MASK(INT_UDN_REFILL) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_SN_STATIC_ACCESS) | \

    (1ULL << INT_ITLB_MISS) | \

    (1ULL << INT_ILL) | \

    (1ULL << INT_GPV) | \

    (1ULL << INT_SN_ACCESS) | \

    (1ULL << INT_IDN_ACCESS) | \

    (1ULL << INT_UDN_ACCESS) | \

    (1ULL << INT_IDN_REFILL) | \

    (1ULL << INT_UDN_REFILL) | \

    (1ULL << INT_IDN_COMPLETE) | \

    (1ULL << INT_UDN_COMPLETE) | \

    (1ULL << INT_SWINT_3) | \

    (1ULL << INT_SWINT_2) | \

    (1ULL << INT_SWINT_1) | \

    (1ULL << INT_SWINT_0) | \

    (1ULL << INT_UNALIGN_DATA) | \

    (1ULL << INT_DTLB_MISS) | \

    (1ULL << INT_DTLB_ACCESS) | \

    (1ULL << INT_SN_STATIC_ACCESS) | \

    0)

#define CRITICAL_MASKED_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_DMATLB_MISS) | \

    INT_MASK(INT_DMATLB_ACCESS) | \

    INT_MASK(INT_SNITLB_MISS) | \

    INT_MASK(INT_SN_NOTIFY) | \

    INT_MASK(INT_SN_FIREWALL) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_DMA_NOTIFY) | \

    INT_MASK(INT_IDN_CA) | \

    INT_MASK(INT_UDN_CA) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    (1ULL << INT_MEM_ERROR) | \

    (1ULL << INT_DMATLB_MISS) | \

    (1ULL << INT_DMATLB_ACCESS) | \

    (1ULL << INT_SNITLB_MISS) | \

    (1ULL << INT_SN_NOTIFY) | \

    (1ULL << INT_SN_FIREWALL) | \

    (1ULL << INT_IDN_FIREWALL) | \

    (1ULL << INT_UDN_FIREWALL) | \

    (1ULL << INT_TILE_TIMER) | \

    (1ULL << INT_IDN_TIMER) | \

    (1ULL << INT_UDN_TIMER) | \

    (1ULL << INT_DMA_NOTIFY) | \

    (1ULL << INT_IDN_CA) | \

    (1ULL << INT_UDN_CA) | \

    (1ULL << INT_IDN_AVAIL) | \

    (1ULL << INT_UDN_AVAIL) | \

    (1ULL << INT_PERF_COUNT) | \

    (1ULL << INT_INTCTRL_3) | \

    (1ULL << INT_INTCTRL_2) | \

    (1ULL << INT_INTCTRL_1) | \

    (1ULL << INT_INTCTRL_0) | \

    (1ULL << INT_AUX_PERF_COUNT) | \

    0)

#define CRITICAL_UNMASKED_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_SN_ACCESS) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_IDN_REFILL) | \

    INT_MASK(INT_UDN_REFILL) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DMA_ASID) | \

    INT_MASK(INT_SNI_ASID) | \

    INT_MASK(INT_DMA_CPL) | \

    INT_MASK(INT_SN_CPL) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    INT_MASK(INT_SN_STATIC_ACCESS) | \

    (1ULL << INT_ITLB_MISS) | \

    (1ULL << INT_ILL) | \

    (1ULL << INT_GPV) | \

    (1ULL << INT_SN_ACCESS) | \

    (1ULL << INT_IDN_ACCESS) | \

    (1ULL << INT_UDN_ACCESS) | \

    (1ULL << INT_IDN_REFILL) | \

    (1ULL << INT_UDN_REFILL) | \

    (1ULL << INT_IDN_COMPLETE) | \

    (1ULL << INT_UDN_COMPLETE) | \

    (1ULL << INT_SWINT_3) | \

    (1ULL << INT_SWINT_2) | \

    (1ULL << INT_SWINT_1) | \

    (1ULL << INT_SWINT_0) | \

    (1ULL << INT_UNALIGN_DATA) | \

    (1ULL << INT_DTLB_MISS) | \

    (1ULL << INT_DTLB_ACCESS) | \

    (1ULL << INT_BOOT_ACCESS) | \

    (1ULL << INT_WORLD_ACCESS) | \

    (1ULL << INT_I_ASID) | \

    (1ULL << INT_D_ASID) | \

    (1ULL << INT_DMA_ASID) | \

    (1ULL << INT_SNI_ASID) | \

    (1ULL << INT_DMA_CPL) | \

    (1ULL << INT_SN_CPL) | \

    (1ULL << INT_DOUBLE_FAULT) | \

    (1ULL << INT_SN_STATIC_ACCESS) | \

    0)

#define MASKABLE_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_IDN_REFILL) | \

    INT_MASK(INT_UDN_REFILL) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_DMATLB_MISS) | \

    INT_MASK(INT_DMATLB_ACCESS) | \

    INT_MASK(INT_SNITLB_MISS) | \

    INT_MASK(INT_SN_NOTIFY) | \

    INT_MASK(INT_SN_FIREWALL) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_DMA_NOTIFY) | \

    INT_MASK(INT_IDN_CA) | \

    INT_MASK(INT_UDN_CA) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    (1ULL << INT_MEM_ERROR) | \

    (1ULL << INT_IDN_REFILL) | \

    (1ULL << INT_UDN_REFILL) | \

    (1ULL << INT_IDN_COMPLETE) | \

    (1ULL << INT_UDN_COMPLETE) | \

    (1ULL << INT_DMATLB_MISS) | \

    (1ULL << INT_DMATLB_ACCESS) | \

    (1ULL << INT_SNITLB_MISS) | \

    (1ULL << INT_SN_NOTIFY) | \

    (1ULL << INT_SN_FIREWALL) | \

    (1ULL << INT_IDN_FIREWALL) | \

    (1ULL << INT_UDN_FIREWALL) | \

    (1ULL << INT_TILE_TIMER) | \

    (1ULL << INT_IDN_TIMER) | \

    (1ULL << INT_UDN_TIMER) | \

    (1ULL << INT_DMA_NOTIFY) | \

    (1ULL << INT_IDN_CA) | \

    (1ULL << INT_UDN_CA) | \

    (1ULL << INT_IDN_AVAIL) | \

    (1ULL << INT_UDN_AVAIL) | \

    (1ULL << INT_PERF_COUNT) | \

    (1ULL << INT_INTCTRL_3) | \

    (1ULL << INT_INTCTRL_2) | \

    (1ULL << INT_INTCTRL_1) | \

    (1ULL << INT_INTCTRL_0) | \

    (1ULL << INT_AUX_PERF_COUNT) | \

    0)

#define UNMASKABLE_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_SN_ACCESS) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DMA_ASID) | \

    INT_MASK(INT_SNI_ASID) | \

    INT_MASK(INT_DMA_CPL) | \

    INT_MASK(INT_SN_CPL) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    INT_MASK(INT_SN_STATIC_ACCESS) | \

    (1ULL << INT_ITLB_MISS) | \

    (1ULL << INT_ILL) | \

    (1ULL << INT_GPV) | \

    (1ULL << INT_SN_ACCESS) | \

    (1ULL << INT_IDN_ACCESS) | \

    (1ULL << INT_UDN_ACCESS) | \

    (1ULL << INT_SWINT_3) | \

    (1ULL << INT_SWINT_2) | \

    (1ULL << INT_SWINT_1) | \

    (1ULL << INT_SWINT_0) | \

    (1ULL << INT_UNALIGN_DATA) | \

    (1ULL << INT_DTLB_MISS) | \

    (1ULL << INT_DTLB_ACCESS) | \

    (1ULL << INT_BOOT_ACCESS) | \

    (1ULL << INT_WORLD_ACCESS) | \

    (1ULL << INT_I_ASID) | \

    (1ULL << INT_D_ASID) | \

    (1ULL << INT_DMA_ASID) | \

    (1ULL << INT_SNI_ASID) | \

    (1ULL << INT_DMA_CPL) | \

    (1ULL << INT_SN_CPL) | \

    (1ULL << INT_DOUBLE_FAULT) | \

    (1ULL << INT_SN_STATIC_ACCESS) | \

    0)

#define SYNC_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_SN_ACCESS) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_IDN_REFILL) | \

    INT_MASK(INT_UDN_REFILL) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_SN_STATIC_ACCESS) | \

    (1ULL << INT_ITLB_MISS) | \

    (1ULL << INT_ILL) | \

    (1ULL << INT_GPV) | \

    (1ULL << INT_SN_ACCESS) | \

    (1ULL << INT_IDN_ACCESS) | \

    (1ULL << INT_UDN_ACCESS) | \

    (1ULL << INT_IDN_REFILL) | \

    (1ULL << INT_UDN_REFILL) | \

    (1ULL << INT_IDN_COMPLETE) | \

    (1ULL << INT_UDN_COMPLETE) | \

    (1ULL << INT_SWINT_3) | \

    (1ULL << INT_SWINT_2) | \

    (1ULL << INT_SWINT_1) | \

    (1ULL << INT_SWINT_0) | \

    (1ULL << INT_UNALIGN_DATA) | \

    (1ULL << INT_DTLB_MISS) | \

    (1ULL << INT_DTLB_ACCESS) | \

    (1ULL << INT_SN_STATIC_ACCESS) | \

    0)

#define NON_SYNC_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_DMATLB_MISS) | \

    INT_MASK(INT_DMATLB_ACCESS) | \

    INT_MASK(INT_SNITLB_MISS) | \

    INT_MASK(INT_SN_NOTIFY) | \

    INT_MASK(INT_SN_FIREWALL) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_DMA_NOTIFY) | \

    INT_MASK(INT_IDN_CA) | \

    INT_MASK(INT_UDN_CA) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DMA_ASID) | \

    INT_MASK(INT_SNI_ASID) | \

    INT_MASK(INT_DMA_CPL) | \

    INT_MASK(INT_SN_CPL) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    (1ULL << INT_MEM_ERROR) | \

    (1ULL << INT_DMATLB_MISS) | \

    (1ULL << INT_DMATLB_ACCESS) | \

    (1ULL << INT_SNITLB_MISS) | \

    (1ULL << INT_SN_NOTIFY) | \

    (1ULL << INT_SN_FIREWALL) | \

    (1ULL << INT_IDN_FIREWALL) | \

    (1ULL << INT_UDN_FIREWALL) | \

    (1ULL << INT_TILE_TIMER) | \

    (1ULL << INT_IDN_TIMER) | \

    (1ULL << INT_UDN_TIMER) | \

    (1ULL << INT_DMA_NOTIFY) | \

    (1ULL << INT_IDN_CA) | \

    (1ULL << INT_UDN_CA) | \

    (1ULL << INT_IDN_AVAIL) | \

    (1ULL << INT_UDN_AVAIL) | \

    (1ULL << INT_PERF_COUNT) | \

    (1ULL << INT_INTCTRL_3) | \

    (1ULL << INT_INTCTRL_2) | \

    (1ULL << INT_INTCTRL_1) | \

    (1ULL << INT_INTCTRL_0) | \

    (1ULL << INT_BOOT_ACCESS) | \

    (1ULL << INT_WORLD_ACCESS) | \

    (1ULL << INT_I_ASID) | \

    (1ULL << INT_D_ASID) | \

    (1ULL << INT_DMA_ASID) | \

    (1ULL << INT_SNI_ASID) | \

    (1ULL << INT_DMA_CPL) | \

    (1ULL << INT_SN_CPL) | \

    (1ULL << INT_DOUBLE_FAULT) | \

    (1ULL << INT_AUX_PERF_COUNT) | \

    0)

#endif /* !__ASSEMBLER__ */

#endif /* !__ARCH_INTERRUPTS_H__ */

arch/tile/include/uapi/arch/interrupts_64.h

+174 −172

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