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Commit 73ba3a1c authored by Maxime Ripard's avatar Maxime Ripard
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ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate 



In order to be able to properly generate its pixel clock, the pll3-2x fixed
factor needs to be able to change the PLL3 rate too.

Add the needed extra compatible so that it behaves that way.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 6a706356

arch/arm/boot/dts/sun5i.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ 
		};



		pll3x2: pll3x2_clk {

			compatible = "fixed-factor-clock";

			compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";

			#clock-cells = <0>;

			clock-div = <1>;

			clock-mult = <2>;