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Commit 739596b0 authored by Kalle Valo's avatar Kalle Valo
Browse files

Merge tag 'iwlwifi-next-for-kalle-2016-03-02' of... 

Merge tag 'iwlwifi-next-for-kalle-2016-03-02' of https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next

* add support for thermal device / cooling device (Chaya Rachel)
* fixes for 9000 devices data path (Sara Sharon)
* improvements in scheduled scan w/o profiles (Luca)
* new firmware support (-21.ucode)
* add MSIX support for 9000 devices (Haim Dreyfuss)
* cleanup in PCIe initialization
* enable MU-MIMO and take care of firmware restart(Sara Sharon)
        ===> This needs mac80211-next
* add support for large SKBs in mvm to reach A-MSDU
        ===> This needs mac80211-next
* add support for filtering frames from a BA session (Sara Sharon)
        ===> This needs mac80211-next
* start implementing the new Rx path for 9000 devices (Sara Sharon)
* enable the new RRM feature flag (Beni Lev)
* fix U-APSD enablement on P2P Client (Avri Altman)
* fix beacon abort enablement (Avri Altman)
* forbid beacon storing with WoWLAN (Matti Gottlieb)
* support unified uSniffer / regular firmware image (Golan Ben-Ami)
* fix a race between debugfs hooks and iface up (Chaya Rachel Ivgi)
* fixes for runtime PM (Luca)
* add a new module paramater to disable VHT (Andrei Otcheretianski)
* build infrastructure for Dynamic Queue Allocation (Liad Kaufman)
parents 0ea6f0c5 53f09e74

drivers/net/wireless/intel/iwlwifi/iwl-7000.c

+2 −2
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ 
/* Highest firmware API version supported */

#define IWL7260_UCODE_API_MAX	17

#define IWL7265_UCODE_API_MAX	17

#define IWL7265D_UCODE_API_MAX	20

#define IWL3168_UCODE_API_MAX	20

#define IWL7265D_UCODE_API_MAX	21

#define IWL3168_UCODE_API_MAX	21



/* Oldest version we won't warn about */

#define IWL7260_UCODE_API_OK	13

drivers/net/wireless/intel/iwlwifi/iwl-8000.c

+3 −2
Original line number Diff line number Diff line
@@ -70,8 +70,8 @@ 
#include "iwl-agn-hw.h"



/* Highest firmware API version supported */

#define IWL8000_UCODE_API_MAX	20

#define IWL8265_UCODE_API_MAX	20

#define IWL8000_UCODE_API_MAX	21

#define IWL8265_UCODE_API_MAX	21



/* Oldest version we won't warn about */

#define IWL8000_UCODE_API_OK	13
@@ -217,6 +217,7 @@ const struct iwl_cfg iwl8265_2ac_cfg = { 
	.nvm_ver = IWL8000_NVM_VERSION,

	.nvm_calib_ver = IWL8000_TX_POWER_VERSION,

	.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,

	.vht_mu_mimo_supported = true,

};



const struct iwl_cfg iwl4165_2ac_cfg = {

drivers/net/wireless/intel/iwlwifi/iwl-9000.c

+3 −2
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
#include "iwl-agn-hw.h"



/* Highest firmware API version supported */

#define IWL9000_UCODE_API_MAX	20

#define IWL9000_UCODE_API_MAX	21



/* Oldest version we won't warn about */

#define IWL9000_UCODE_API_OK	13
@@ -139,7 +139,8 @@ static const struct iwl_tt_params iwl9000_tt_params = { 
	.smem_len = IWL9000_SMEM_LEN,					\

	.thermal_params = &iwl9000_tt_params,				\

	.apmg_not_supported = true,					\

	.mq_rx_supported = true

	.mq_rx_supported = true,					\

	.vht_mu_mimo_supported = true



const struct iwl_cfg iwl9260_2ac_cfg = {

		.name = "Intel(R) Dual Band Wireless AC 9260",

drivers/net/wireless/intel/iwlwifi/iwl-config.h

+2 −0
Original line number Diff line number Diff line
@@ -312,6 +312,7 @@ struct iwl_pwr_tx_backoff { 
 * @smem_offset: offset from which the SMEM begins

 * @smem_len: the length of SMEM

 * @mq_rx_supported: multi-queue rx support

 * @vht_mu_mimo_supported: VHT MU-MIMO support

 *

 * We enable the driver to be backward compatible wrt. hardware features.

 * API differences in uCode shouldn't be handled here but through TLVs
@@ -364,6 +365,7 @@ struct iwl_cfg { 
	const struct iwl_tt_params *thermal_params;

	bool apmg_not_supported;

	bool mq_rx_supported;

	bool vht_mu_mimo_supported;

};



/*

drivers/net/wireless/intel/iwlwifi/iwl-csr.h

+49 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 *

 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.

 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH

 * Copyright(c) 2016        Intel Deutschland GmbH

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of version 2 of the GNU General Public License as
@@ -549,4 +550,52 @@ enum dtd_diode_reg { 
	DTS_DIODE_REG_FLAGS_PASS_ONCE		= 0x00000080, /* bits [7:7] */

};



/*****************************************************************************

 *                        MSIX related registers                             *

 *****************************************************************************/



#define CSR_MSIX_BASE			(0x2000)

#define CSR_MSIX_FH_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x800)

#define CSR_MSIX_FH_INT_MASK_AD		(CSR_MSIX_BASE + 0x804)

#define CSR_MSIX_HW_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x808)

#define CSR_MSIX_HW_INT_MASK_AD		(CSR_MSIX_BASE + 0x80C)

#define CSR_MSIX_AUTOMASK_ST_AD		(CSR_MSIX_BASE + 0x810)

#define CSR_MSIX_RX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x880)

#define CSR_MSIX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x890)

#define CSR_MSIX_PENDING_PBA_AD		(CSR_MSIX_BASE + 0x1000)

#define CSR_MSIX_RX_IVAR(cause)		(CSR_MSIX_RX_IVAR_AD_REG + (cause))

#define CSR_MSIX_IVAR(cause)		(CSR_MSIX_IVAR_AD_REG + (cause))



#define MSIX_FH_INT_CAUSES_Q(q)		(q)



/*

 * Causes for the FH register interrupts

 */

enum msix_fh_int_causes {

	MSIX_FH_INT_CAUSES_D2S_CH0_NUM		= BIT(16),

	MSIX_FH_INT_CAUSES_D2S_CH1_NUM		= BIT(17),

	MSIX_FH_INT_CAUSES_S2D			= BIT(19),

	MSIX_FH_INT_CAUSES_FH_ERR		= BIT(21),

};



/*

 * Causes for the HW register interrupts

 */

enum msix_hw_int_causes {

	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),

	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),

	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),

	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),

	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),

	MSIX_HW_INT_CAUSES_REG_SW_ERR		= BIT(25),

	MSIX_HW_INT_CAUSES_REG_SCD		= BIT(26),

	MSIX_HW_INT_CAUSES_REG_FH_TX		= BIT(27),

	MSIX_HW_INT_CAUSES_REG_HW_ERR		= BIT(29),

	MSIX_HW_INT_CAUSES_REG_HAP		= BIT(30),

};



#define MSIX_MIN_INTERRUPT_VECTORS		2

#define MSIX_AUTO_CLEAR_CAUSE			0

#define MSIX_NON_AUTO_CLEAR_CAUSE		BIT(7)



#endif /* !__iwl_csr_h__ */