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Commit 72ec9456 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pm-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 

Pull power management updates from Rafael Wysocki:
 "Traditionally, cpufreq is the area with the greatest number of
  changes, but there are fewer of them than last time. There also is
  some activity in the generic power domains and the devfreq frameworks,
  a couple of system suspend and hibernation fixes and some assorted
  changes in other places.

  One new feature is the cpufreq change to allow the scheduler to pass
  hints to the governors' utilization update callbacks and some code
  rework based on that. Another one is the support for domain removal in
  the generic power domains framework. Also it is now possible to use
  hibernation with PAGE_POISONING_ZERO enabled and devfreq supports the
  RockChip DFI controller and the rk3399 DMC.

  The rest of the changes is mostly fixes and cleanups in a number of
  places.

  Specifics:

   - Add a mechanism for passing hints from the scheduler to cpufreq
     governors via their utilization update callbacks and use it to
     introduce "IOwait boosting" into the schedutil governor and
     intel_pstate that will make them boost performance if the enqueued
     task was previously waiting on I/O (Rafael Wysocki).

   - Fix a schedutil governor problem that causes it to overestimate
     utilization if SMT is in use (Steve Muckle).

   - Update defconfigs trying to use the schedutil governor as a module
     which is not possible any more (Javier Martinez Canillas).

   - Update the intel_pstate's pstate_sample tracepoint to take "IOwait
     boosting" into account (Srinivas Pandruvada).

   - Fix a problem in the cpufreq core causing it to mishandle the
     initialization of CPUs registered after the cpufreq driver (Viresh
     Kumar, Rafael Wysocki).

   - Make the cpufreq-dt driver support per-policy governor tunables,
     clean it up and update its Kconfig description (Viresh Kumar).

   - Add support for more ARM platforms to the cpufreq-dt driver
     (Chanwoo Choi, Dave Gerlach, Geert Uytterhoeven).

   - Make the cpufreq CPPC driver report frequencies in KHz to avoid
     user space compatiblility issues (Al Stone, Hoan Tran).

   - Clean up a few cpufreq drivers (st, kirkwood, SCPI) a bit (Colin
     Ian King, Markus Elfring).

   - Constify some local structures in the intel_pstate driver (Julia
     Lawall).

   - Add a Documentation/cpu-freq/ entry to MAINTAINERS (Jean Delvare).

   - Add support for PM domain removal to the generic power domains
     (genpd) framework, add new DT helper functions to it and make it
     always enable debugfs support if available (Jon Hunter, Tomeu
     Vizoso).

   - Clean up the generic power domains (genpd) framework and make it
     avoid measuring power-on and power-off latencies during system-wide
     PM transitions (Ulf Hansson).

   - Add support for the RockChip DFI controller and the rk3399 DMC to
     the devfreq framework (Lin Huang, Axel Lin, Arnd Bergmann).

   - Add COMPILE_TEST to the devfreq framework (Krzysztof Kozlowski,
     Stephen Rothwell).

   - Fix a minor issue in the exynos-ppmu devfreq driver and fix up
     devfreq Kconfig indentation style (Wei Yongjun, Jisheng Zhang).

   - Fix the system suspend interface to make suspend-to-idle work if
     platform suspend operations have not been registered (Sudeep
     Holla).

   - Make it possible to use hibernation with PAGE_POISONING_ZERO
     enabled (Anisse Astier).

   - Increas the default timeout of the system suspend/resume watchdog
     and make it depend on EXPERT (Chen Yu).

   - Make the operating performance points (OPP) framework avoid using
     OPPs that aren't supported by the platform and fix a build warning
     in it (Dave Gerlach, Arnd Bergmann).

   - Fix the ARM cpuidle driver's return value (Christophe Jaillet).

   - Make the SmartReflex AVS (Adaptive Voltage Scaling) driver use more
     common logging style (Joe Perches)"

* tag 'pm-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (58 commits)
  PM / OPP: Don't support OPP if it provides supported-hw but platform does not
  cpufreq: st: add missing \n to end of dev_err message
  cpufreq: kirkwood: add missing \n to end of dev_err messages
  PM / Domains: Rename pm_genpd_sync_poweron|poweroff()
  PM / Domains: Don't measure latency of ->power_on|off() during system PM
  PM / Domains: Remove redundant system PM callbacks
  PM / Domains: Simplify detaching a device from its genpd
  PM / devfreq: rk3399_dmc: Remove explictly regulator_put call in .remove
  PM / devfreq: rockchip: add PM_DEVFREQ_EVENT dependency
  PM / OPP: avoid maybe-uninitialized warning
  PM / Domains: Allow holes in genpd_data.domains array
  cpufreq: CPPC: Avoid overflow when calculating desired_perf
  cpufreq: ti: Use generic platdev driver
  cpufreq: intel_pstate: Add io_boost trace
  partial revert of "PM / devfreq: Add COMPILE_TEST for build coverage"
  cpufreq: intel_pstate: Use IOWAIT flag in Atom algorithm
  cpufreq: schedutil: Add iowait boosting
  cpufreq / sched: SCHED_CPUFREQ_IOWAIT flag to indicate iowait condition
  PM / Domains: Add support for removing nested PM domains by provider
  PM / Domains: Add support for removing PM domains
  ...
parents 7af8a0f8 993eb0ae

Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt

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* Rockchip rk3399 DFI device



Required properties:

- compatible: Must be "rockchip,rk3399-dfi".

- reg: physical base address of each DFI and length of memory mapped region

- rockchip,pmu: phandle to the syscon managing the "pmu general register files"

- clocks: phandles for clock specified in "clock-names" property

- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";



Example:

	dfi: dfi@0xff630000 {

		compatible = "rockchip,rk3399-dfi";

		reg = <0x00 0xff630000 0x00 0x4000>;

		rockchip,pmu = <&pmugrf>;

		clocks = <&cru PCLK_DDR_MON>;

		clock-names = "pclk_ddr_mon";

		status = "disabled";

	};

Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

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* Rockchip rk3399 DMC(Dynamic Memory Controller) device



Required properties:

- compatible:		 Must be "rockchip,rk3399-dmc".

- devfreq-events:	 Node to get DDR loading, Refer to

			 Documentation/devicetree/bindings/devfreq/

			 rockchip-dfi.txt

- interrupts:		 The interrupt number to the CPU. The interrupt

			 specifier format depends on the interrupt controller.

			 It should be DCF interrupts, when DDR dvfs finish,

			 it will happen.

- clocks:		 Phandles for clock specified in "clock-names" property

- clock-names :		 The name of clock used by the DFI, must be

			 "pclk_ddr_mon";

- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt

			 for details.

- center-supply:	 DMC supply node.

- status:		 Marks the node enabled/disabled.



Following properties are ddr timing:



- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/ddr.h,

				  it select ddr3 cl-trp-trcd type, default value

				  "DDR3_DEFAULT".it must selected according to

				  "Speed Bin" in ddr3 datasheet, DO NOT use

				  smaller "Speed Bin" than ddr3 exactly is.



- rockchip,pd_idle :		  Config the PD_IDLE value, defined the power-down

				  idle period, memories are places into power-down

				  mode if bus is idle for PD_IDLE DFI clocks.



- rockchip,sr_idle :		  Configure the SR_IDLE value, defined the

				  selfrefresh idle period, memories are places

				  into self-refresh mode if bus is idle for

				  SR_IDLE*1024 DFI clocks (DFI clocks freq is

				  half of dram's clocks), defaule value is "0".



- rockchip,sr_mc_gate_idle :	  Defined the self-refresh with memory and

				  controller clock gating idle period, memories

				  are places into self-refresh mode and memory

				  controller clock arg gating if bus is idle for

				  sr_mc_gate_idle*1024 DFI clocks.



- rockchip,srpd_lite_idle :	  Defined the self-refresh power down idle

				  period, memories are places into self-refresh

				  power down mode if bus is idle for

				  srpd_lite_idle*1024 DFI clocks. This parameter

				  is for LPDDR4 only.



- rockchip,standby_idle :	  Defined the standby idle period, memories are

				  places into self-refresh than controller, pi,

				  phy and dram clock will gating if bus is idle

				  for standby_idle * DFI clocks.



- rockchip,dram_dll_disb_freq :  It's defined the DDR3 dll bypass frequency in

				  MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,

				  ddr3 dll will bypssed note: if dll was bypassed,

				  the odt also stop working.



- rockchip,phy_dll_disb_freq :	  Defined the PHY dll bypass frequency in

				  MHz (Mega Hz), when ddr freq less than

				  DRAM_DLL_DISB_FREQ, phy dll will bypssed.

				  note: phy dll and phy odt are independent.



- rockchip,ddr3_odt_disb_freq :  When dram type is DDR3, this parameter defined

				  the odt disable frequency in MHz (Mega Hz),

				  when ddr frequency less then ddr3_odt_disb_freq,

				  the odt on dram side and controller side are

				  both disabled.



- rockchip,ddr3_drv :		  When dram type is DDR3, this parameter define

				  the dram side driver stength in ohm, default

				  value is DDR3_DS_40ohm.



- rockchip,ddr3_odt :		  When dram type is DDR3, this parameter define

				  the dram side ODT stength in ohm, default value

				  is DDR3_ODT_120ohm.



- rockchip,phy_ddr3_ca_drv :	  When dram type is DDR3, this parameter define

				  the phy side CA line(incluing command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.



- rockchip,phy_ddr3_dq_drv :	  When dram type is DDR3, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is PHY_DRV_ODT_40.



- rockchip,phy_ddr3_odt : 	  When dram type is DDR3, this parameter define the

				  phy side odt strength, default value is

				  PHY_DRV_ODT_240.



- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined

				  then odt disable frequency in MHz (Mega Hz),

				  when ddr frequency less then ddr3_odt_disb_freq,

				  the odt on dram side and controller side are

				  both disabled.



- rockchip,lpddr3_drv :	  When dram type is LPDDR3, this parameter define

				  the dram side driver stength in ohm, default

				  value is LP3_DS_34ohm.



- rockchip,lpddr3_odt :	  When dram type is LPDDR3, this parameter define

				  the dram side ODT stength in ohm, default value

				  is LP3_ODT_240ohm.



- rockchip,phy_lpddr3_ca_drv :	  When dram type is LPDDR3, this parameter define

				  the phy side CA line(incluing command line,

				  address line and clock line) driver strength.

				  default value is PHY_DRV_ODT_40.



- rockchip,phy_lpddr3_dq_drv :	  When dram type is LPDDR3, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is

				  PHY_DRV_ODT_40.



- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define

				  the phy side odt strength, default value is

				  PHY_DRV_ODT_240.



- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter

				  defined the odt disable frequency in

				  MHz (Mega Hz), when ddr frequency less then

				  ddr3_odt_disb_freq, the odt on dram side and

				  controller side are both disabled.



- rockchip,lpddr4_drv :	  When dram type is LPDDR4, this parameter define

				  the dram side driver stength in ohm, default

				  value is LP4_PDDS_60ohm.



- rockchip,lpddr4_dq_odt : 	  When dram type is LPDDR4, this parameter define

				  the dram side ODT on dqs/dq line stength in ohm,

				  default value is LP4_DQ_ODT_40ohm.



- rockchip,lpddr4_ca_odt :	  When dram type is LPDDR4, this parameter define

				  the dram side ODT on ca line stength in ohm,

				  default value is LP4_CA_ODT_40ohm.



- rockchip,phy_lpddr4_ca_drv :	  When dram type is LPDDR4, this parameter define

				  the phy side  CA line(incluing command address

				  line) driver strength. default value is

				  PHY_DRV_ODT_40.



- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define

				  the phy side clock line and cs line driver

				  strength. default value is PHY_DRV_ODT_80.



- rockchip,phy_lpddr4_dq_drv :	  When dram type is LPDDR4, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is PHY_DRV_ODT_80.



- rockchip,phy_lpddr4_odt :	  When dram type is LPDDR4, this parameter define

				  the phy side odt strength, default value is

				  PHY_DRV_ODT_60.



Example:

	dmc_opp_table: dmc_opp_table {

		compatible = "operating-points-v2";



		opp00 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <900000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <666000000>;

			opp-microvolt = <900000>;

		};

	};



	dmc: dmc {

		compatible = "rockchip,rk3399-dmc";

		devfreq-events = <&dfi>;

		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_DDRCLK>;

		clock-names = "dmc_clk";

		operating-points-v2 = <&dmc_opp_table>;

		center-supply = <&ppvar_centerlogic>;

		upthreshold = <15>;

		downdifferential = <10>;

		rockchip,ddr3_speed_bin = <21>;

		rockchip,pd_idle = <0x40>;

		rockchip,sr_idle = <0x2>;

		rockchip,sr_mc_gate_idle = <0x3>;

		rockchip,srpd_lite_idle	= <0x4>;

		rockchip,standby_idle = <0x2000>;

		rockchip,dram_dll_dis_freq = <300>;

		rockchip,phy_dll_dis_freq = <125>;

		rockchip,auto_pd_dis_freq = <666>;

		rockchip,ddr3_odt_dis_freq = <333>;

		rockchip,ddr3_drv = <DDR3_DS_40ohm>;

		rockchip,ddr3_odt = <DDR3_ODT_120ohm>;

		rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,lpddr3_odt_dis_freq = <333>;

		rockchip,lpddr3_drv = <LP3_DS_34ohm>;

		rockchip,lpddr3_odt = <LP3_ODT_240ohm>;

		rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,lpddr4_odt_dis_freq = <333>;

		rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;

		rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;

		rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;

		rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;

		status = "disabled";

	};

MAINTAINERS

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@@ -3284,6 +3284,7 @@ L: linux-pm@vger.kernel.org 
S:	Maintained

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git

T:	git git://git.linaro.org/people/vireshk/linux.git (For ARM Updates)

F:	Documentation/cpu-freq/

F:	drivers/cpufreq/

F:	include/linux/cpufreq.h

arch/arm/configs/exynos_defconfig

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@@ -28,7 +28,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 
CONFIG_CPU_FREQ_GOV_POWERSAVE=m

CONFIG_CPU_FREQ_GOV_USERSPACE=m

CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m

CONFIG_CPU_FREQ_GOV_SCHEDUTIL=m

CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

CONFIG_CPUFREQ_DT=y

CONFIG_CPU_IDLE=y

CONFIG_ARM_EXYNOS_CPUIDLE=y

arch/arm/configs/multi_v7_defconfig

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@@ -135,7 +135,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 
CONFIG_CPU_FREQ_GOV_POWERSAVE=m

CONFIG_CPU_FREQ_GOV_USERSPACE=m

CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m

CONFIG_CPU_FREQ_GOV_SCHEDUTIL=m

CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

CONFIG_QORIQ_CPUFREQ=y

CONFIG_CPU_IDLE=y

CONFIG_ARM_CPUIDLE=y