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Commit 727b8124 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
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ARM: dts: i.MX51: Separate TXD/RXD and RTS/CTS pinmux entries for UARTs 



RTS/CTS pins can be used for different purposes, so create separate
definitions for these pins.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 44a26877

arch/arm/boot/dts/imx51-babbage.dts

+2 −2
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ 


&uart3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart3_1>;

	pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;

	fsl,uart-has-rtscts;

	status = "okay";

};
@@ -252,7 +252,7 @@ 


&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1_1>;

	pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;

	fsl,uart-has-rtscts;

	status = "okay";

};

arch/arm/boot/dts/imx51.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -747,6 +747,11 @@ 
			fsl,pins = <

				MX51_PAD_UART1_RXD__UART1_RXD 0x1c5

				MX51_PAD_UART1_TXD__UART1_TXD 0x1c5

			>;

		};



		pinctrl_uart1_rtscts_1: uart1rtscts-1 {

			fsl,pins = <

				MX51_PAD_UART1_RTS__UART1_RTS 0x1c5

				MX51_PAD_UART1_CTS__UART1_CTS 0x1c5

			>;
@@ -767,6 +772,11 @@ 
			fsl,pins = <

				MX51_PAD_EIM_D25__UART3_RXD 0x1c5

				MX51_PAD_EIM_D26__UART3_TXD 0x1c5

			>;

		};



		pinctrl_uart3_rtscts_1: uart3rtscts-1 {

			fsl,pins = <

				MX51_PAD_EIM_D27__UART3_RTS 0x1c5

				MX51_PAD_EIM_D24__UART3_CTS 0x1c5

			>;