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Commit 72419203 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: hw state readout support for fdi m/n 



We want to use the fdi m/n values to easily compute the adjusted mode
dotclock on pch ports. Hence make sure the values stored in the pipe
config are always reliable.

v2: Fixup FDI TU readout.

v3: Rebase on top of moved cpu_transcoder.

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 08a24034

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -2776,6 +2776,7 @@ 
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */

#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)

#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25

#define  TU_SIZE_SHIFT		25



#define   PIPE_GMCH_DATA_M_MASK			(0xffffff)

drivers/gpu/drm/i915/intel_display.c

+25 −0
Original line number Diff line number Diff line
@@ -5817,6 +5817,22 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	return ret;

}



static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,

					struct intel_crtc_config *pipe_config)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum transcoder transcoder = pipe_config->cpu_transcoder;



	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));

	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));

	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))

					& ~TU_SIZE_MASK;

	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));

	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))

				   & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;

}



static bool ironlake_get_pipe_config(struct intel_crtc *crtc,

				     struct intel_crtc_config *pipe_config)

{
@@ -5834,6 +5850,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 
		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));

		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

					  FDI_DP_PORT_WIDTH_SHIFT) + 1;



		ironlake_get_fdi_m_n_config(crtc, pipe_config);

	}



	return true;
@@ -5979,6 +5997,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
		tmp = I915_READ(FDI_RX_CTL(PIPE_A));

		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

					  FDI_DP_PORT_WIDTH_SHIFT) + 1;



		ironlake_get_fdi_m_n_config(crtc, pipe_config);

	}



	return true;
@@ -7960,6 +7980,11 @@ intel_pipe_config_compare(struct intel_crtc_config *current_config, 


	PIPE_CONF_CHECK_I(has_pch_encoder);

	PIPE_CONF_CHECK_I(fdi_lanes);

	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);

	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);

	PIPE_CONF_CHECK_I(fdi_m_n.link_m);

	PIPE_CONF_CHECK_I(fdi_m_n.link_n);

	PIPE_CONF_CHECK_I(fdi_m_n.tu);



#undef PIPE_CONF_CHECK_I