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Commit 7164f4c5 authored by Roy Spliet's avatar Roy Spliet Committed by Ben Skeggs
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drm/nouveau/bios/rammap: Pull DLLoff bit out of version 0x10 struct 



In preparation of NV50 reclocking, where there is no version

Signed-off-by: default avatarRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 4a68ccc8

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h

+1 −1
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ struct nvbios_ramcfg { 
	unsigned ramcfg_ver;

	unsigned ramcfg_hdr;

	unsigned ramcfg_timing;

	unsigned ramcfg_DLLoff;

	union {

		struct {

			unsigned ramcfg_10_02_01:1;
@@ -40,7 +41,6 @@ struct nvbios_ramcfg { 
			unsigned ramcfg_10_02_08:1;

			unsigned ramcfg_10_02_10:1;

			unsigned ramcfg_10_02_20:1;

			unsigned ramcfg_10_DLLoff:1;

			unsigned ramcfg_10_03_0f:4;

			unsigned ramcfg_10_04_01:1;

			unsigned ramcfg_10_05:8;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c

+1 −1
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ nvbios_rammapSp(struct nvkm_bios *bios, u32 data, 
		p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;

		p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;

		p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;

		p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;

		p->ramcfg_DLLoff   = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;

		p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;

		p->ramcfg_10_04_01 = (nv_ro08(bios, data + 0x04) & 0x01) >> 0;

		p->ramcfg_10_05    = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c

+1 −1
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram) 
		CWL = ram->next->bios.timing_10_CWL;

		CL  = ram->next->bios.timing_10_CL;

		WR  = ram->next->bios.timing_10_WR;

		DLL = !ram->next->bios.ramcfg_10_DLLoff;

		DLL = !ram->next->bios.ramcfg_DLLoff;

		ODT = ram->next->bios.timing_10_ODT;

		break;

	case 0x20:

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c

+3 −3
Original line number Diff line number Diff line
@@ -590,7 +590,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) 
		r100da0 = 0x00000000;

	}



	if (!next->bios.ramcfg_10_DLLoff)

	if (!next->bios.ramcfg_DLLoff)

		r004018 |= 0x00004000;



	/* pll2pll requires to switch to a safe clock first */
@@ -630,7 +630,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) 
	}



	/* If we're disabling the DLL, do it now */

	switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {

	switch (next->bios.ramcfg_DLLoff * ram->base.type) {

	case NV_MEM_TYPE_DDR3:

		nvkm_sddr3_dll_disable(fuc, ram->base.mr);

		break;
@@ -810,7 +810,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) 
		gt215_ram_fbvref(fuc, 1);



	/* Reset DLL */

	if (!next->bios.ramcfg_10_DLLoff)

	if (!next->bios.ramcfg_DLLoff)

		nvkm_sddr2_dll_reset(fuc);



	if (ram->base.type == NV_MEM_TYPE_GDDR3) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ nvkm_sddr2_calc(struct nvkm_ram *ram) 
	case 0x10:

		CL  = ram->next->bios.timing_10_CL;

		WR  = ram->next->bios.timing_10_WR;

		DLL = !ram->next->bios.ramcfg_10_DLLoff;

		DLL = !ram->next->bios.ramcfg_DLLoff;

		ODT = ram->next->bios.timing_10_ODT & 3;

		break;

	case 0x20: