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Commit 7098fc03 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "Merge android-4.9.226(92339d65) into msm-4.9"

parents 3447e207 0fa749ab

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 9

SUBLEVEL = 225

SUBLEVEL = 226

EXTRAVERSION =

NAME = Roaring Lionus

arch/arm/boot/dts/imx6q-b450v3.dts

+0 −7
Original line number Diff line number Diff line
@@ -65,13 +65,6 @@ 
	};

};



&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,

				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

};



&ldb {

	status = "okay";

arch/arm/boot/dts/imx6q-b650v3.dts

+0 −7
Original line number Diff line number Diff line
@@ -65,13 +65,6 @@ 
	};

};



&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,

				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

};



&ldb {

	status = "okay";

arch/arm/boot/dts/imx6q-b850v3.dts

+0 −11
Original line number Diff line number Diff line
@@ -53,17 +53,6 @@ 
	};

};



&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;

};



&ldb {

	fsl,dual-channel;

	status = "okay";

arch/arm/boot/dts/imx6q-bx50v3.dtsi

+77 −0
Original line number Diff line number Diff line
@@ -92,6 +92,56 @@ 
		mux-int-port = <1>;

		mux-ext-port = <4>;

	};



	aliases {

		mdio-gpio0 = &mdio0;

	};



	mdio0: mdio-gpio {

		compatible = "virtual,mdio-gpio";

		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */

			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */



		#address-cells = <1>;

		#size-cells = <0>;



		switch@0 {

			compatible = "marvell,mv88e6085"; /* 88e6240*/

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;



			switch_ports: ports {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				switchphy0: switchphy@0 {

					reg = <0>;

				};



				switchphy1: switchphy@1 {

					reg = <1>;

				};



				switchphy2: switchphy@2 {

					reg = <2>;

				};



				switchphy3: switchphy@3 {

					reg = <3>;

				};



				switchphy4: switchphy@4 {

					reg = <4>;

				};

			};

		};

	};

};



&ecspi5 {
@@ -299,3 +349,30 @@ 
		tcxo-clock-frequency = <26000000>;

	};

};



&pcie {

	/* Synopsys, Inc. Device */

	pci_root: root@0,0 {

		compatible = "pci16c3,abcd";

		reg = <0x00000000 0 0 0 0>;



		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

	};

};



&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,

			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,

			  <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,

				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,

				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,

				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;

};