Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 70855bb5 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

clk: sunxi: Allow to specify the divider width from the dividers data 



The divider width used to be hardcoded. Some A31 dividers are no longer
with the hardcoded width, so we need to make it specific to each divider
and set it in the dividers data.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: default avatarEmilio López <emilio@elopez.com.ar>
parent 81ba6c5e

drivers/clk/sunxi/clk-sunxi.c

+13 −11
Original line number Diff line number Diff line
@@ -279,26 +279,28 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, 
 * sunxi_divider_clk_setup() - Setup function for simple divider clocks

 */



#define SUNXI_DIVISOR_WIDTH	2



struct div_data {

	u8	shift;

	u8	pow;

	u8	width;

};



static const __initconst struct div_data sun4i_axi_data = {

	.shift	= 0,

	.pow	= 0,

	.width	= 2,

};



static const __initconst struct div_data sun4i_ahb_data = {

	.shift	= 4,

	.pow	= 1,

	.width	= 2,

};



static const __initconst struct div_data sun4i_apb0_data = {

	.shift	= 8,

	.pow	= 1,

	.width	= 2,

};



static void __init sunxi_divider_clk_setup(struct device_node *node,
@@ -314,7 +316,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, 
	clk_parent = of_clk_get_parent_name(node, 0);



	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,

				   reg, data->shift, SUNXI_DIVISOR_WIDTH,

				   reg, data->shift, data->width,

				   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,

				   &clk_lock);

	if (clk) {