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Commit 7083e42e authored by Shani Michaeli's avatar Shani Michaeli Committed by Roland Dreier
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IB/core: Add "type 2" memory windows support 



This patch enhances the IB core support for Memory Windows (MWs).

MWs allow an application to have better/flexible control over remote
access to memory.

Two types of MWs are supported, with the second type having two flavors:

    Type 1  - associated with PD only
    Type 2A - associated with QPN only
    Type 2B - associated with PD and QPN

Applications can allocate a MW once, and then repeatedly bind the MW
to different ranges in MRs that are associated to the same PD. Type 1
windows are bound through a verb, while type 2 windows are bound by
posting a work request.

The 32-bit memory key is composed of a 24-bit index and an 8-bit
key. The key is changed with each bind, thus allowing more control
over the peer's use of the memory key.

The changes introduced are the following:

* add memory window type enum and a corresponding parameter to ib_alloc_mw.
* type 2 memory window bind work request support.
* create a struct that contains the common part of the bind verb struct
  ibv_mw_bind and the bind work request into a single struct.
* add the ib_inc_rkey helper function to advance the tag part of an rkey.

Consumer interface details:

* new device capability flags IB_DEVICE_MEM_WINDOW_TYPE_2A and
  IB_DEVICE_MEM_WINDOW_TYPE_2B are added to indicate device support
  for these features.

  Devices can set either IB_DEVICE_MEM_WINDOW_TYPE_2A or
  IB_DEVICE_MEM_WINDOW_TYPE_2B if it supports type 2A or type 2B
  memory windows. It can set neither to indicate it doesn't support
  type 2 windows at all.

* modify existing provides and consumers code to the new param of
  ib_alloc_mw and the ib_mw_bind_info structure

Signed-off-by: default avatarHaggai Eran <haggaie@mellanox.com>
Signed-off-by: default avatarShani Michaeli <shanim@mellanox.com>
Signed-off-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarRoland Dreier <roland@purestorage.com>
parent 836dc9e3

drivers/infiniband/core/verbs.c

+3 −2
Original line number Diff line number Diff line
@@ -1099,18 +1099,19 @@ EXPORT_SYMBOL(ib_free_fast_reg_page_list); 


/* Memory windows */



struct ib_mw *ib_alloc_mw(struct ib_pd *pd)

struct ib_mw *ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type)

{

	struct ib_mw *mw;



	if (!pd->device->alloc_mw)

		return ERR_PTR(-ENOSYS);



	mw = pd->device->alloc_mw(pd);

	mw = pd->device->alloc_mw(pd, type);

	if (!IS_ERR(mw)) {

		mw->device  = pd->device;

		mw->pd      = pd;

		mw->uobject = NULL;

		mw->type    = type;

		atomic_inc(&pd->usecnt);

	}

drivers/infiniband/hw/cxgb3/iwch_provider.c

+4 −1
Original line number Diff line number Diff line
@@ -738,7 +738,7 @@ static struct ib_mr *iwch_get_dma_mr(struct ib_pd *pd, int acc) 
	return ibmr;

}



static struct ib_mw *iwch_alloc_mw(struct ib_pd *pd)

static struct ib_mw *iwch_alloc_mw(struct ib_pd *pd, enum ib_mw_type type)

{

	struct iwch_dev *rhp;

	struct iwch_pd *php;
@@ -747,6 +747,9 @@ static struct ib_mw *iwch_alloc_mw(struct ib_pd *pd) 
	u32 stag = 0;

	int ret;



	if (type != IB_MW_TYPE_1)

		return ERR_PTR(-EINVAL);



	php = to_iwch_pd(pd);

	rhp = php->rhp;

	mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);

drivers/infiniband/hw/cxgb3/iwch_qp.c

+8 −7
Original line number Diff line number Diff line
@@ -567,18 +567,19 @@ int iwch_bind_mw(struct ib_qp *qp, 
	if (mw_bind->send_flags & IB_SEND_SIGNALED)

		t3_wr_flags = T3_COMPLETION_FLAG;



	sgl.addr = mw_bind->addr;

	sgl.lkey = mw_bind->mr->lkey;

	sgl.length = mw_bind->length;

	sgl.addr = mw_bind->bind_info.addr;

	sgl.lkey = mw_bind->bind_info.mr->lkey;

	sgl.length = mw_bind->bind_info.length;

	wqe->bind.reserved = 0;

	wqe->bind.type = TPT_VATO;



	/* TBD: check perms */

	wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags);

	wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);

	wqe->bind.perms = iwch_ib_to_tpt_bind_access(

		mw_bind->bind_info.mw_access_flags);

	wqe->bind.mr_stag = cpu_to_be32(mw_bind->bind_info.mr->lkey);

	wqe->bind.mw_stag = cpu_to_be32(mw->rkey);

	wqe->bind.mw_len = cpu_to_be32(mw_bind->length);

	wqe->bind.mw_va = cpu_to_be64(mw_bind->addr);

	wqe->bind.mw_len = cpu_to_be32(mw_bind->bind_info.length);

	wqe->bind.mw_va = cpu_to_be64(mw_bind->bind_info.addr);

	err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);

	if (err) {

		spin_unlock_irqrestore(&qhp->lock, flag);

drivers/infiniband/hw/cxgb4/iw_cxgb4.h

+1 −1
Original line number Diff line number Diff line
@@ -866,7 +866,7 @@ struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 
					int page_list_len);

struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);

int c4iw_dealloc_mw(struct ib_mw *mw);

struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);

struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);

struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,

					   u64 length, u64 virt, int acc,

					   struct ib_udata *udata);

drivers/infiniband/hw/cxgb4/mem.c

+4 −1
Original line number Diff line number Diff line
@@ -650,7 +650,7 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 
	return ERR_PTR(err);

}



struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd)

struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type)

{

	struct c4iw_dev *rhp;

	struct c4iw_pd *php;
@@ -659,6 +659,9 @@ struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd) 
	u32 stag = 0;

	int ret;



	if (type != IB_MW_TYPE_1)

		return ERR_PTR(-EINVAL);



	php = to_c4iw_pd(pd);

	rhp = php->rhp;

	mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);