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Commit 6fa2d197 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Jani Nikula
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i915: Set ddi_pll_sel in DP MST path 

The DP MST encoder config function never sets ddi_pll_sel, even though
its value is programmed in its ->pre_enable() hook. That used to work
because a new pipe_config was kzalloc'ed at every modeset, and the value
of zero selects the highest clock for the PLL. Starting with the commit
below, the value of ddi_pll_sel is preserved through modesets, and since
the correct value wasn't properly setup by the MST code, it could lead
to warnings and blank screens.

commit 8504c74c
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Fri May 15 11:51:50 2015 +0300

    drm/i915: Preserve ddi_pll_sel when allocating new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628


Cc: stable@vger.kernel.org # 7e6313a2 drm/i915: Don't use link_bw for PLL setup
Cc: stable@vger.kernel.org
Cc: Timo Aaltonen <tjaalton@ubuntu.com>
Cc: Luciano Coelho <luciano.coelho@intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 7e6313a2

drivers/gpu/drm/i915/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -1175,7 +1175,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) 
	pipe_config->dpll_hw_state.ctrl1 = ctrl1;

}



static void

void

hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)

{

	memset(&pipe_config->dpll_hw_state, 0,

drivers/gpu/drm/i915/intel_dp_mst.c

+5 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,

					struct intel_crtc_state *pipe_config)

{

	struct drm_device *dev = encoder->base.dev;

	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);

	struct intel_digital_port *intel_dig_port = intel_mst->primary;

	struct intel_dp *intel_dp = &intel_dig_port->dp;
@@ -97,6 +98,10 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 
			       &pipe_config->dp_m_n);



	pipe_config->dp_m_n.tu = slots;



	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		hsw_dp_set_ddi_pll_sel(pipe_config);



	return true;



}

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1185,6 +1185,7 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp); 
void intel_edp_drrs_invalidate(struct drm_device *dev,

		unsigned frontbuffer_bits);

void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);

void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);



/* intel_dp_mst.c */

int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);