Merge "msm: ep_pcie: Perform pcie controller reset before MHI mmio restore" (6f97a37b) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+34 −34

Original line number	Diff line number	Diff line
		@@ -1342,17 +1342,12 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
		}

		dev->power_on = true;
		}

		if (!(opt & EP_PCIE_OPT_ENUM))
		goto out;

		/* check link status during initial bootup */
		if (!dev->enumerated) {
		val = readl_relaxed(dev->parf + PCIE20_PARF_PM_STTS);
		val = val & PARF_XMLH_LINK_UP;
		EP_PCIE_DBG(dev, "PCIe V%d: Link status is 0x%x.\n", dev->rev,
		val);
		EP_PCIE_DBG(dev, "PCIe V%d: Link status is 0x%x.\n",
		dev->rev, val);
		if (val) {
		EP_PCIE_INFO(dev,
		"PCIe V%d: link initialized by bootloader for LE PCIe endpoint; skip link training in HLOS.\n",
		@@ -1379,6 +1374,14 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
		}
		}

		ret = ep_pcie_reset_init(dev);
		if (ret)
		goto link_fail;
		}

		if (!(opt & EP_PCIE_OPT_ENUM))
		goto out;

		if (opt & EP_PCIE_OPT_AST_WAKE) {
		/* assert PCIe WAKE# */
		EP_PCIE_INFO(dev, "PCIe V%d: assert PCIe WAKE#.\n",
		@@ -1430,9 +1433,6 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
		}
		}

		ret = ep_pcie_reset_init(dev);
		if (ret)
		goto link_fail;
		/* init PCIe PHY */
		ep_pcie_phy_init(dev);