Commit 6f67fe7a authored Nov 28, 2017 by Hemant Kumar

ARM: dts: msm: Add super speed phy reset clocks for sdxpoorwills



Super speed phy needs to perform BCR reset using GCC_USB3_PHY_BCR
and GCC_USB3PHY_PHY_BCR.

Change-Id: I05be3c42d8d6195e639dc75679d4118adee10ec6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>

parent 01c25b13

arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -215,5 +215,8 @@

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
		"cfg_ahb_clk";
		resets = <&clock_gcc GCC_USB3_PHY_BCR>,
		<&clock_gcc GCC_USB3PHY_PHY_BCR>;
		reset-names = "phy_reset", "phy_phy_reset";
		};
		};