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Commit 6f10b4e1 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Kalle Valo
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wcn36xx: Correct DXE chip version differentiation



The CCU block in WCNSS is configured for appropriate routing of
interrupts from the DXE to the application cpu, this is not dependant on
the iris version (wcn3660 vs wcn3680), but rather if the SoC has a riva
or pronto built in.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 05ddce49
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+6 −5
Original line number Diff line number Diff line
@@ -702,12 +702,13 @@ int wcn36xx_dxe_init(struct wcn36xx *wcn)
	reg_data = WCN36XX_DXE_REG_RESET;
	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);

	/* Setting interrupt path */
	reg_data = WCN36XX_DXE_CCU_INT;
	if (wcn->chip_version == WCN36XX_CHIP_3680)
		wcn36xx_ccu_write_register(wcn, WCN36XX_DXE_REG_CCU_INT_3680, reg_data);
	/* Select channels for rx avail and xfer done interrupts... */
	reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 |
		    WCN36XX_DXE_INT_CH0_MASK | WCN36XX_DXE_INT_CH4_MASK;
	if (wcn->is_pronto)
		wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data);
	else
		wcn36xx_ccu_write_register(wcn, WCN36XX_DXE_REG_CCU_INT_3660, reg_data);
		wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data);

	/***************************************/
	/* Init descriptors for TX LOW channel */
+2 −3
Original line number Diff line number Diff line
@@ -30,9 +30,8 @@ H2H_TEST_RX_TX = DMA2
/* DXE registers */
#define WCN36XX_DXE_MEM_REG			0

#define WCN36XX_DXE_CCU_INT			0xA0011
#define WCN36XX_DXE_REG_CCU_INT_3660		0x310
#define WCN36XX_DXE_REG_CCU_INT_3680		0x10dc
#define WCN36XX_CCU_DXE_INT_SELECT_RIVA		0x310
#define WCN36XX_CCU_DXE_INT_SELECT_PRONTO	0x10dc

/* TODO This must calculated properly but not hardcoded */
#define WCN36XX_DXE_CTRL_TX_L			0x328a44
+2 −14
Original line number Diff line number Diff line
@@ -261,17 +261,6 @@ static void wcn36xx_feat_caps_info(struct wcn36xx *wcn)
	}
}

static void wcn36xx_detect_chip_version(struct wcn36xx *wcn)
{
	if (get_feat_caps(wcn->fw_feat_caps, DOT11AC)) {
		wcn36xx_info("Chip is 3680\n");
		wcn->chip_version = WCN36XX_CHIP_3680;
	} else {
		wcn36xx_info("Chip is 3660\n");
		wcn->chip_version = WCN36XX_CHIP_3660;
	}
}

static int wcn36xx_start(struct ieee80211_hw *hw)
{
	struct wcn36xx *wcn = hw->priv;
@@ -326,9 +315,6 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
			wcn36xx_feat_caps_info(wcn);
	}

	wcn36xx_detect_chip_version(wcn);
	wcn36xx_smd_update_cfg(wcn, WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST, 1);

	/* DMA channel initialization */
	ret = wcn36xx_dxe_init(wcn);
	if (ret) {
@@ -1095,6 +1081,8 @@ static int wcn36xx_platform_get_resources(struct wcn36xx *wcn,
		return -EINVAL;
	}

	wcn->is_pronto = !!of_device_is_compatible(mmio_node, "qcom,pronto");

	/* Map the CCU memory */
	index = of_property_match_string(mmio_node, "reg-names", "ccu");
	wcn->ccu_base = of_iomap(mmio_node, index);
+1 −4
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ struct wcn36xx {
	u8			fw_minor;
	u8			fw_major;
	u32			fw_feat_caps[WCN36XX_HAL_CAPS_SIZE];
	u32			chip_version;
	bool			is_pronto;

	/* extra byte for the NULL termination */
	u8			crm_version[WCN36XX_HAL_VERSION_LENGTH + 1];
@@ -242,9 +242,6 @@ struct wcn36xx {

};

#define WCN36XX_CHIP_3660	0
#define WCN36XX_CHIP_3680	1

static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
					 u8 major,
					 u8 minor,