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Commit 6f0508d3 authored Apr 28, 2017 by Padmanabhan Komanduru

clk: qcom: mdss: add upstream clock framework support for 10nm DP PLL



Model and configure the 10nm MDSS Display Port PLL for SDM845. Add
change to define the clocks and their relevant ops for DP VCO,
divider and mux using upstream clock framework.

Change-Id: If190a18cb6ec900c8bf5d93604d1d288aeee243d
Signed-off-by: Govinda Rajulu Chenna <gchenna@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

parent 3e269fe3

Documentation/devicetree/bindings/fb/mdss-pll.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@ Required properties:
		"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
		"qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8",
		"qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998",
		"qcom,mdss_hdmi_pll_8998"
		"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm".
		- cell-index: Specifies the controller used
		- reg: offset and length of the register set for the device.
		- reg-names : names to refer to register sets related to this device

drivers/clk/qcom/mdss/Makefile

+3 −0

Original line number	Diff line number	Diff line
		obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll-util.o
		obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll.o
		obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-10nm.o
		obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm.o
		obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm-util.o

drivers/clk/qcom/mdss/mdss-dp-pll-10nm-util.c

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drivers/clk/qcom/mdss/mdss-dp-pll-10nm.c

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drivers/clk/qcom/mdss/mdss-dp-pll-10nm.h

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