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Commit 6f041e3f authored by Ping Li's avatar Ping Li
Browse files

drm/msm/sde: Correct IRQ mapping table for AD 



IRQ dispatcher expects each interrupt register has a range of 32
indexes. This change adds reserved IRQ for AD0 and AD1 backlight
interrupts to match the expected 32 range indexes.

CRs-Fixed: 2093305
Change-Id: I973bac03af30213a27937809ec40c330ccb1b3ca
Signed-off-by: default avatarPing Li <pingli@codeaurora.org>
parent 089d1cb5

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+82 −2
Original line number Diff line number Diff line
@@ -682,9 +682,89 @@ static const struct sde_irq_type sde_irq_map[] = { 
	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 7},



	/* irq_idx: 256-257 */

	/* BEGIN MAP_RANGE: 256-287 AD4_0_INTR */

	/* irq_idx: 256-259 */

	{ SDE_IRQ_TYPE_AD4_BL_DONE, DSPP_0, SDE_INTR_BACKLIGHT_UPDATED, 8},

	{ SDE_IRQ_TYPE_AD4_BL_DONE, DSPP_1, SDE_INTR_BACKLIGHT_UPDATED, 9}

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 260-263 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 264-267 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 268-271 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 272-275 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 276-279 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 280-283 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	/* irq_idx: 284-287 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 8},



	/* BEGIN MAP_RANGE: 288-319 AD4_1_INTR */

	/* irq_idx: 288-291 */

	{ SDE_IRQ_TYPE_AD4_BL_DONE, DSPP_1, SDE_INTR_BACKLIGHT_UPDATED, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 292-295 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 296-299 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 300-303 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 304-307 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 308-311 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 312-315 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	/* irq_idx: 315-319 */

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 9},

};



static int sde_hw_intr_irqidx_lookup(enum sde_intr_type intr_type,