Loading drivers/gpu/msm/kgsl_gmu.c +9 −0 Original line number Diff line number Diff line Loading @@ -807,6 +807,15 @@ static irqreturn_t gmu_irq_handler(int irq, void *data) if (status & GMU_INT_HOST_AHB_BUS_ERR) dev_err_ratelimited(&gmu->pdev->dev, "AHB bus error interrupt received\n"); if (status & GMU_INT_FENCE_ERR) { unsigned int fence_status; adreno_read_gmureg(ADRENO_DEVICE(device), ADRENO_REG_GMU_AHB_FENCE_STATUS, &fence_status); dev_err_ratelimited(&gmu->pdev->dev, "FENCE error interrupt received %x\n", fence_status); } if (status & ~GMU_AO_INT_MASK) dev_err_ratelimited(&gmu->pdev->dev, "Unhandled GMU interrupts 0x%lx\n", Loading drivers/gpu/msm/kgsl_gmu.h +3 −1 Original line number Diff line number Diff line Loading @@ -22,11 +22,13 @@ #define GMU_INT_WDOG_BITE BIT(0) #define GMU_INT_RSCC_COMP BIT(1) #define GMU_INT_FENCE_ERR BIT(3) #define GMU_INT_DBD_WAKEUP BIT(4) #define GMU_INT_HOST_AHB_BUS_ERR BIT(5) #define GMU_AO_INT_MASK \ (GMU_INT_WDOG_BITE | \ GMU_INT_HOST_AHB_BUS_ERR) GMU_INT_HOST_AHB_BUS_ERR | \ GMU_INT_FENCE_ERR) #define MAX_GMUFW_SIZE 0x2000 /* in dwords */ #define FENCE_RANGE_MASK ((0x1 << 31) | (0x0A << 18) | (0x8A0)) Loading Loading
drivers/gpu/msm/kgsl_gmu.c +9 −0 Original line number Diff line number Diff line Loading @@ -807,6 +807,15 @@ static irqreturn_t gmu_irq_handler(int irq, void *data) if (status & GMU_INT_HOST_AHB_BUS_ERR) dev_err_ratelimited(&gmu->pdev->dev, "AHB bus error interrupt received\n"); if (status & GMU_INT_FENCE_ERR) { unsigned int fence_status; adreno_read_gmureg(ADRENO_DEVICE(device), ADRENO_REG_GMU_AHB_FENCE_STATUS, &fence_status); dev_err_ratelimited(&gmu->pdev->dev, "FENCE error interrupt received %x\n", fence_status); } if (status & ~GMU_AO_INT_MASK) dev_err_ratelimited(&gmu->pdev->dev, "Unhandled GMU interrupts 0x%lx\n", Loading
drivers/gpu/msm/kgsl_gmu.h +3 −1 Original line number Diff line number Diff line Loading @@ -22,11 +22,13 @@ #define GMU_INT_WDOG_BITE BIT(0) #define GMU_INT_RSCC_COMP BIT(1) #define GMU_INT_FENCE_ERR BIT(3) #define GMU_INT_DBD_WAKEUP BIT(4) #define GMU_INT_HOST_AHB_BUS_ERR BIT(5) #define GMU_AO_INT_MASK \ (GMU_INT_WDOG_BITE | \ GMU_INT_HOST_AHB_BUS_ERR) GMU_INT_HOST_AHB_BUS_ERR | \ GMU_INT_FENCE_ERR) #define MAX_GMUFW_SIZE 0x2000 /* in dwords */ #define FENCE_RANGE_MASK ((0x1 << 31) | (0x0A << 18) | (0x8A0)) Loading