Loading drivers/gpu/drm/msm/sde/sde_encoder.c +45 −58 Original line number Diff line number Diff line Loading @@ -571,17 +571,9 @@ void sde_encoder_schedule_kickoff(struct drm_encoder *drm_enc, static int sde_encoder_virt_add_phys_encs( u32 display_caps, struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role) struct sde_enc_phys_init_params *params) { struct sde_encoder_phys *enc = NULL; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; DBG(""); Loading @@ -597,8 +589,7 @@ static int sde_encoder_virt_add_phys_encs( } if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { enc = sde_encoder_phys_vid_init(sde_kms, intf_idx, ctl_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_vid_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys vid enc: %ld\n", Loading @@ -611,9 +602,7 @@ static int sde_encoder_virt_add_phys_encs( } if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { enc = sde_encoder_phys_cmd_init(sde_kms, intf_idx, pp_idx, ctl_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_cmd_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys cmd enc: %ld\n", Loading @@ -628,32 +617,20 @@ static int sde_encoder_virt_add_phys_encs( return 0; } static int sde_encoder_virt_add_phys_enc_wb( struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role) static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc, struct sde_enc_phys_init_params *params) { struct sde_encoder_phys *enc = NULL; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; DBG(""); if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) { if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) { DRM_ERROR("Too many physical encoders %d, unable to add\n", sde_enc->num_phys_encs); return -EINVAL; } enc = sde_encoder_phys_wb_init(sde_kms, wb_idx, ctl_idx, cdm_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_wb_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys wb enc: %ld\n", Loading @@ -674,7 +651,17 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, { int ret = 0; int i = 0; enum sde_intf_type intf_type = INTF_NONE; enum sde_intf_type intf_type; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; struct sde_enc_phys_init_params phys_params; memset(&phys_params, 0, sizeof(phys_params)); phys_params.sde_kms = sde_kms; phys_params.parent = &sde_enc->base; phys_params.parent_ops = parent_ops; DBG(""); Loading Loading @@ -703,63 +690,63 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right */ const struct sde_hw_res_map *hw_res_map = NULL; enum sde_intf intf_idx = INTF_MAX; enum sde_pingpong pp_idx = PINGPONG_MAX; enum sde_wb wb_idx = WB_MAX; enum sde_ctl ctl_idx = CTL_MAX; enum sde_cdm cdm_idx = SDE_NONE; u32 controller_id = disp_info->h_tile_instance[i]; enum sde_enc_split_role split_role = ENC_ROLE_SOLO; if (disp_info->num_of_h_tiles > 1) { if (i == 0) split_role = ENC_ROLE_MASTER; phys_params.split_role = ENC_ROLE_MASTER; else split_role = ENC_ROLE_SLAVE; phys_params.split_role = ENC_ROLE_SLAVE; } else { phys_params.split_role = ENC_ROLE_SOLO; } DBG("h_tile_instance %d = %d, split_role %d", i, controller_id, split_role); i, controller_id, phys_params.split_role); if (intf_type == INTF_WB) { wb_idx = sde_encoder_get_wb(sde_kms->catalog, phys_params.wb_idx = sde_encoder_get_wb( sde_kms->catalog, intf_type, controller_id); if (wb_idx == WB_MAX) { if (phys_params.wb_idx == WB_MAX) { DRM_ERROR( "Error: could not get the writeback id\n"); "Error: could not get writeback: type %d, id %d\n", intf_type, controller_id); ret = -EINVAL; } intf_idx = SDE_NONE; } else { intf_idx = sde_encoder_get_intf(sde_kms->catalog, intf_type, controller_id); if (intf_idx == INTF_MAX) { phys_params.intf_idx = sde_encoder_get_intf( sde_kms->catalog, intf_type, controller_id); if (phys_params.intf_idx == INTF_MAX) { DRM_ERROR( "Error: could not get the interface id\n"); "Error: could not get writeback: type %d, id %d\n", intf_type, controller_id); ret = -EINVAL; } wb_idx = SDE_NONE; } hw_res_map = sde_rm_get_res_map(sde_kms, intf_idx, wb_idx); hw_res_map = sde_rm_get_res_map(sde_kms, phys_params.intf_idx, phys_params.wb_idx); if (IS_ERR_OR_NULL(hw_res_map)) { DRM_ERROR("failed to get hw_res_map: %ld\n", PTR_ERR(hw_res_map)); ret = -EINVAL; } else { pp_idx = hw_res_map->pp; ctl_idx = hw_res_map->ctl; cdm_idx = hw_res_map->cdm; phys_params.pp_idx = hw_res_map->pp; phys_params.ctl_idx = hw_res_map->ctl; phys_params.cdm_idx = hw_res_map->cdm; } if (!ret) { if (intf_type == INTF_WB) ret = sde_encoder_virt_add_phys_enc_wb( sde_enc, sde_kms, wb_idx, ctl_idx, cdm_idx, split_role); ret = sde_encoder_virt_add_phys_enc_wb(sde_enc, &phys_params); else ret = sde_encoder_virt_add_phys_encs( disp_info->capabilities, sde_enc, sde_kms, intf_idx, pp_idx, ctl_idx, split_role); sde_enc, &phys_params); if (ret) DRM_ERROR("Failed to add phys encs\n"); } Loading drivers/gpu/drm/msm/sde/sde_encoder_phys.h +29 −46 Original line number Diff line number Diff line Loading @@ -242,74 +242,57 @@ struct sde_encoder_phys_wb { }; /** * sde_encoder_phys_vid_init - Construct a new video mode physical encoder * struct sde_enc_phys_init_params - initialization parameters for phys encs * @sde_kms: Pointer to the sde_kms top level * @intf_idx: Interface index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * @split_role: Role to play in a split-panel configuration * @intf_idx: Interface index this phys_enc will control * @wb_idx: Writeback index this phys_enc will control * @pp_idx: Pingpong index this phys_enc will control * @ctl_idx: Control path index this phys_enc will use * @cdm_idx: Chromadown index this phys_enc will use */ struct sde_enc_phys_init_params { struct sde_kms *sde_kms; struct drm_encoder *parent; struct sde_encoder_virt_ops parent_ops; enum sde_enc_split_role split_role; enum sde_intf intf_idx; enum sde_wb wb_idx; enum sde_pingpong pp_idx; enum sde_ctl ctl_idx; enum sde_cdm cdm_idx; }; /** * sde_encoder_phys_vid_init - Construct a new video mode physical encoder * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ struct sde_encoder_phys *sde_encoder_phys_vid_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); /** * sde_encoder_phys_cmd_init - Construct a new command mode physical encoder * @sde_kms: Pointer to the sde_kms top level * @intf_idx: Interface index this phys_enc will control * @pp_idx: PingPong index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ struct sde_encoder_phys *sde_encoder_phys_cmd_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); /** * sde_encoder_phys_wb_init - Construct a new writeback physical encoder * @sde_kms: Pointer to the sde_kms top level * @wb_idx: Writeback index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @cdm_idx: Chromadown index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ #ifdef CONFIG_DRM_SDE_WB struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); #else static inline struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { return NULL; } Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +13 −19 Original line number Diff line number Diff line Loading @@ -439,19 +439,13 @@ static void sde_encoder_phys_cmd_init_ops( } struct sde_encoder_phys *sde_encoder_phys_cmd_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc = NULL; struct sde_encoder_phys_cmd *cmd_enc = NULL; int ret = 0; DBG("intf %d, pp %d", intf_idx, pp_idx); DBG("intf %d, pp %d", p->intf_idx, p->pp_idx); cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL); if (!cmd_enc) { Loading @@ -460,8 +454,8 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( } phys_enc = &cmd_enc->base; phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(phys_enc->hw_mdptop)) { ret = PTR_ERR(phys_enc->hw_mdptop); phys_enc->hw_mdptop = NULL; Loading @@ -469,11 +463,11 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( goto fail_mdptop; } cmd_enc->intf_idx = intf_idx; cmd_enc->intf_idx = p->intf_idx; phys_enc->hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (phys_enc->hw_ctl == ERR_PTR(-ENODEV)) phys_enc->hw_ctl = sde_rm_get_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_get_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { ret = PTR_ERR(phys_enc->hw_ctl); Loading @@ -482,8 +476,8 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( goto fail_ctl; } cmd_enc->hw_pp = sde_hw_pingpong_init(pp_idx, sde_kms->mmio, sde_kms->catalog); cmd_enc->hw_pp = sde_hw_pingpong_init(p->pp_idx, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(cmd_enc->hw_pp)) { ret = PTR_ERR(cmd_enc->hw_pp); cmd_enc->hw_pp = NULL; Loading @@ -492,10 +486,10 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( } sde_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); phys_enc->mode_3d = BLEND_3D_NONE; cmd_enc->stream_sel = 0; Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +12 −17 Original line number Diff line number Diff line Loading @@ -602,18 +602,13 @@ static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops) } struct sde_encoder_phys *sde_encoder_phys_vid_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc = NULL; struct sde_encoder_phys_vid *vid_enc = NULL; int ret = 0; DBG("intf %d", intf_idx); DBG("intf %d", p->intf_idx); vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL); if (!vid_enc) { Loading @@ -625,8 +620,8 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( phys_enc = &vid_enc->base; phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(phys_enc->hw_mdptop)) { ret = PTR_ERR(phys_enc->hw_mdptop); phys_enc->hw_mdptop = NULL; Loading @@ -634,8 +629,8 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( goto fail; } vid_enc->hw_intf = sde_hw_intf_init(intf_idx, sde_kms->mmio, sde_kms->catalog); vid_enc->hw_intf = sde_hw_intf_init(p->intf_idx, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(vid_enc->hw_intf)) { ret = PTR_ERR(vid_enc->hw_intf); vid_enc->hw_intf = NULL; Loading @@ -648,9 +643,9 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( * will both try to get it, depending on which is first need to call * acquire (initial), and other one needs to call get (add ref count) */ phys_enc->hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (phys_enc->hw_ctl == ERR_PTR(-ENODEV)) phys_enc->hw_ctl = sde_rm_get_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_get_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { ret = PTR_ERR(phys_enc->hw_ctl); Loading @@ -660,10 +655,10 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( } sde_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); init_completion(&vid_enc->vblank_completion); Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +28 −39 Original line number Diff line number Diff line Loading @@ -886,22 +886,10 @@ static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops) /** * sde_encoder_phys_wb_init - initialize writeback encoder * @sde_kms: Pointer to SDE KMS object * @wb_idx: Writeback index * @ctl_idx: Control index * @cdm_idx: Chroma down index * @split_role: Master/slave mode * @parent: Pointer to virtual encoder * @parent_ops: Pointer to virtual encoder operations * @init: Pointer to init info structure with initialization params */ struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc; struct sde_encoder_phys_wb *wb_enc; Loading @@ -921,19 +909,20 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( phys_enc = &wb_enc->base; if (sde_kms->vbif[VBIF_NRT]) { if (p->sde_kms->vbif[VBIF_NRT]) { wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE]; wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE]; } else { wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE]; } hw_mdp = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); hw_mdp = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(hw_mdp)) { ret = PTR_ERR(hw_mdp); SDE_ERROR("failed to init hw_top: %d\n", ret); Loading @@ -941,15 +930,15 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( } phys_enc->hw_mdptop = hw_mdp; if (wb_idx != SDE_NONE) { if (p->wb_idx != SDE_NONE) { struct sde_hw_wb *hw_wb; hw_wb = sde_hw_wb_init(wb_idx, sde_kms->mmio, sde_kms->catalog, phys_enc->hw_mdptop); hw_wb = sde_hw_wb_init(p->wb_idx, p->sde_kms->mmio, p->sde_kms->catalog, phys_enc->hw_mdptop); if (IS_ERR_OR_NULL(hw_wb)) { ret = PTR_ERR(hw_wb); SDE_ERROR("failed to init hw_wb%d: %d\n", wb_idx - WB_0, ret); p->wb_idx - WB_0, ret); goto fail_wb_init; } wb_enc->hw_wb = hw_wb; Loading @@ -959,30 +948,30 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( goto fail_wb_check; } if (cdm_idx != SDE_NONE) { if (p->cdm_idx != SDE_NONE) { struct sde_hw_cdm *hw_cdm; SDE_DEBUG("Acquiring CDM %d\n", cdm_idx - CDM_0); hw_cdm = sde_rm_acquire_cdm_path(sde_kms, cdm_idx, SDE_DEBUG("Acquiring CDM %d\n", p->cdm_idx - CDM_0); hw_cdm = sde_rm_acquire_cdm_path(p->sde_kms, p->cdm_idx, phys_enc->hw_mdptop); if (IS_ERR_OR_NULL(hw_cdm)) { ret = PTR_ERR(hw_cdm); SDE_ERROR("failed to init hw_cdm%d: %d\n", cdm_idx - CDM_0, ret); p->cdm_idx - CDM_0, ret); goto fail_cdm_init; } phys_enc->hw_cdm = hw_cdm; } if (ctl_idx != SDE_NONE) { if (p->ctl_idx != SDE_NONE) { struct sde_hw_ctl *hw_ctl; SDE_DEBUG("Acquiring CTL %d\n", ctl_idx - CTL_0); hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); SDE_DEBUG("Acquiring CTL %d\n", p->ctl_idx - CTL_0); hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(hw_ctl)) { ret = PTR_ERR(hw_ctl); SDE_ERROR("failed to init hw_ctl%d: %d\n", ctl_idx - CTL_0, ret); p->ctl_idx - CTL_0, ret); goto fail_ctl_init; } phys_enc->hw_ctl = hw_ctl; Loading @@ -993,13 +982,13 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( } sde_encoder_phys_wb_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); ret = sde_encoder_phys_wb_init_debugfs(phys_enc, sde_kms); ret = sde_encoder_phys_wb_init_debugfs(phys_enc, p->sde_kms); if (ret) { SDE_ERROR("failed to init debugfs %d\n", ret); goto fail_debugfs_init; Loading @@ -1011,10 +1000,10 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( return phys_enc; fail_debugfs_init: sde_rm_release_ctl_path(sde_kms, ctl_idx); sde_rm_release_ctl_path(p->sde_kms, p->ctl_idx); fail_ctl_init: fail_ctl_check: sde_rm_release_cdm_path(sde_kms, cdm_idx); sde_rm_release_cdm_path(p->sde_kms, p->cdm_idx); fail_cdm_init: sde_hw_wb_destroy(wb_enc->hw_wb); fail_wb_init: Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +45 −58 Original line number Diff line number Diff line Loading @@ -571,17 +571,9 @@ void sde_encoder_schedule_kickoff(struct drm_encoder *drm_enc, static int sde_encoder_virt_add_phys_encs( u32 display_caps, struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role) struct sde_enc_phys_init_params *params) { struct sde_encoder_phys *enc = NULL; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; DBG(""); Loading @@ -597,8 +589,7 @@ static int sde_encoder_virt_add_phys_encs( } if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { enc = sde_encoder_phys_vid_init(sde_kms, intf_idx, ctl_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_vid_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys vid enc: %ld\n", Loading @@ -611,9 +602,7 @@ static int sde_encoder_virt_add_phys_encs( } if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { enc = sde_encoder_phys_cmd_init(sde_kms, intf_idx, pp_idx, ctl_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_cmd_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys cmd enc: %ld\n", Loading @@ -628,32 +617,20 @@ static int sde_encoder_virt_add_phys_encs( return 0; } static int sde_encoder_virt_add_phys_enc_wb( struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role) static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc, struct sde_enc_phys_init_params *params) { struct sde_encoder_phys *enc = NULL; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; DBG(""); if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) { if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) { DRM_ERROR("Too many physical encoders %d, unable to add\n", sde_enc->num_phys_encs); return -EINVAL; } enc = sde_encoder_phys_wb_init(sde_kms, wb_idx, ctl_idx, cdm_idx, split_role, &sde_enc->base, parent_ops); enc = sde_encoder_phys_wb_init(params); if (IS_ERR_OR_NULL(enc)) { DRM_ERROR("Failed to initialize phys wb enc: %ld\n", Loading @@ -674,7 +651,17 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, { int ret = 0; int i = 0; enum sde_intf_type intf_type = INTF_NONE; enum sde_intf_type intf_type; struct sde_encoder_virt_ops parent_ops = { sde_encoder_vblank_callback, sde_encoder_handle_phys_enc_ready_for_kickoff }; struct sde_enc_phys_init_params phys_params; memset(&phys_params, 0, sizeof(phys_params)); phys_params.sde_kms = sde_kms; phys_params.parent = &sde_enc->base; phys_params.parent_ops = parent_ops; DBG(""); Loading Loading @@ -703,63 +690,63 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc, * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right */ const struct sde_hw_res_map *hw_res_map = NULL; enum sde_intf intf_idx = INTF_MAX; enum sde_pingpong pp_idx = PINGPONG_MAX; enum sde_wb wb_idx = WB_MAX; enum sde_ctl ctl_idx = CTL_MAX; enum sde_cdm cdm_idx = SDE_NONE; u32 controller_id = disp_info->h_tile_instance[i]; enum sde_enc_split_role split_role = ENC_ROLE_SOLO; if (disp_info->num_of_h_tiles > 1) { if (i == 0) split_role = ENC_ROLE_MASTER; phys_params.split_role = ENC_ROLE_MASTER; else split_role = ENC_ROLE_SLAVE; phys_params.split_role = ENC_ROLE_SLAVE; } else { phys_params.split_role = ENC_ROLE_SOLO; } DBG("h_tile_instance %d = %d, split_role %d", i, controller_id, split_role); i, controller_id, phys_params.split_role); if (intf_type == INTF_WB) { wb_idx = sde_encoder_get_wb(sde_kms->catalog, phys_params.wb_idx = sde_encoder_get_wb( sde_kms->catalog, intf_type, controller_id); if (wb_idx == WB_MAX) { if (phys_params.wb_idx == WB_MAX) { DRM_ERROR( "Error: could not get the writeback id\n"); "Error: could not get writeback: type %d, id %d\n", intf_type, controller_id); ret = -EINVAL; } intf_idx = SDE_NONE; } else { intf_idx = sde_encoder_get_intf(sde_kms->catalog, intf_type, controller_id); if (intf_idx == INTF_MAX) { phys_params.intf_idx = sde_encoder_get_intf( sde_kms->catalog, intf_type, controller_id); if (phys_params.intf_idx == INTF_MAX) { DRM_ERROR( "Error: could not get the interface id\n"); "Error: could not get writeback: type %d, id %d\n", intf_type, controller_id); ret = -EINVAL; } wb_idx = SDE_NONE; } hw_res_map = sde_rm_get_res_map(sde_kms, intf_idx, wb_idx); hw_res_map = sde_rm_get_res_map(sde_kms, phys_params.intf_idx, phys_params.wb_idx); if (IS_ERR_OR_NULL(hw_res_map)) { DRM_ERROR("failed to get hw_res_map: %ld\n", PTR_ERR(hw_res_map)); ret = -EINVAL; } else { pp_idx = hw_res_map->pp; ctl_idx = hw_res_map->ctl; cdm_idx = hw_res_map->cdm; phys_params.pp_idx = hw_res_map->pp; phys_params.ctl_idx = hw_res_map->ctl; phys_params.cdm_idx = hw_res_map->cdm; } if (!ret) { if (intf_type == INTF_WB) ret = sde_encoder_virt_add_phys_enc_wb( sde_enc, sde_kms, wb_idx, ctl_idx, cdm_idx, split_role); ret = sde_encoder_virt_add_phys_enc_wb(sde_enc, &phys_params); else ret = sde_encoder_virt_add_phys_encs( disp_info->capabilities, sde_enc, sde_kms, intf_idx, pp_idx, ctl_idx, split_role); sde_enc, &phys_params); if (ret) DRM_ERROR("Failed to add phys encs\n"); } Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys.h +29 −46 Original line number Diff line number Diff line Loading @@ -242,74 +242,57 @@ struct sde_encoder_phys_wb { }; /** * sde_encoder_phys_vid_init - Construct a new video mode physical encoder * struct sde_enc_phys_init_params - initialization parameters for phys encs * @sde_kms: Pointer to the sde_kms top level * @intf_idx: Interface index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * @split_role: Role to play in a split-panel configuration * @intf_idx: Interface index this phys_enc will control * @wb_idx: Writeback index this phys_enc will control * @pp_idx: Pingpong index this phys_enc will control * @ctl_idx: Control path index this phys_enc will use * @cdm_idx: Chromadown index this phys_enc will use */ struct sde_enc_phys_init_params { struct sde_kms *sde_kms; struct drm_encoder *parent; struct sde_encoder_virt_ops parent_ops; enum sde_enc_split_role split_role; enum sde_intf intf_idx; enum sde_wb wb_idx; enum sde_pingpong pp_idx; enum sde_ctl ctl_idx; enum sde_cdm cdm_idx; }; /** * sde_encoder_phys_vid_init - Construct a new video mode physical encoder * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ struct sde_encoder_phys *sde_encoder_phys_vid_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); /** * sde_encoder_phys_cmd_init - Construct a new command mode physical encoder * @sde_kms: Pointer to the sde_kms top level * @intf_idx: Interface index this phys_enc will control * @pp_idx: PingPong index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ struct sde_encoder_phys *sde_encoder_phys_cmd_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); /** * sde_encoder_phys_wb_init - Construct a new writeback physical encoder * @sde_kms: Pointer to the sde_kms top level * @wb_idx: Writeback index this phys_enc will control * @ctl_idx: Control index this phys_enc requires * @cdm_idx: Chromadown index this phys_enc requires * @split_role: Role to play in a split-panel configuration * @parent: Pointer to the containing virtual encoder * @parent_ops: Callbacks exposed by the parent to the phys_enc * * @p: Pointer to init params structure * Return: Error code or newly allocated encoder */ #ifdef CONFIG_DRM_SDE_WB struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops); struct sde_enc_phys_init_params *p); #else static inline struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { return NULL; } Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +13 −19 Original line number Diff line number Diff line Loading @@ -439,19 +439,13 @@ static void sde_encoder_phys_cmd_init_ops( } struct sde_encoder_phys *sde_encoder_phys_cmd_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_pingpong pp_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc = NULL; struct sde_encoder_phys_cmd *cmd_enc = NULL; int ret = 0; DBG("intf %d, pp %d", intf_idx, pp_idx); DBG("intf %d, pp %d", p->intf_idx, p->pp_idx); cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL); if (!cmd_enc) { Loading @@ -460,8 +454,8 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( } phys_enc = &cmd_enc->base; phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(phys_enc->hw_mdptop)) { ret = PTR_ERR(phys_enc->hw_mdptop); phys_enc->hw_mdptop = NULL; Loading @@ -469,11 +463,11 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( goto fail_mdptop; } cmd_enc->intf_idx = intf_idx; cmd_enc->intf_idx = p->intf_idx; phys_enc->hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (phys_enc->hw_ctl == ERR_PTR(-ENODEV)) phys_enc->hw_ctl = sde_rm_get_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_get_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { ret = PTR_ERR(phys_enc->hw_ctl); Loading @@ -482,8 +476,8 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( goto fail_ctl; } cmd_enc->hw_pp = sde_hw_pingpong_init(pp_idx, sde_kms->mmio, sde_kms->catalog); cmd_enc->hw_pp = sde_hw_pingpong_init(p->pp_idx, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(cmd_enc->hw_pp)) { ret = PTR_ERR(cmd_enc->hw_pp); cmd_enc->hw_pp = NULL; Loading @@ -492,10 +486,10 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init( } sde_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); phys_enc->mode_3d = BLEND_3D_NONE; cmd_enc->stream_sel = 0; Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +12 −17 Original line number Diff line number Diff line Loading @@ -602,18 +602,13 @@ static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops) } struct sde_encoder_phys *sde_encoder_phys_vid_init( struct sde_kms *sde_kms, enum sde_intf intf_idx, enum sde_ctl ctl_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc = NULL; struct sde_encoder_phys_vid *vid_enc = NULL; int ret = 0; DBG("intf %d", intf_idx); DBG("intf %d", p->intf_idx); vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL); if (!vid_enc) { Loading @@ -625,8 +620,8 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( phys_enc = &vid_enc->base; phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); phys_enc->hw_mdptop = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(phys_enc->hw_mdptop)) { ret = PTR_ERR(phys_enc->hw_mdptop); phys_enc->hw_mdptop = NULL; Loading @@ -634,8 +629,8 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( goto fail; } vid_enc->hw_intf = sde_hw_intf_init(intf_idx, sde_kms->mmio, sde_kms->catalog); vid_enc->hw_intf = sde_hw_intf_init(p->intf_idx, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(vid_enc->hw_intf)) { ret = PTR_ERR(vid_enc->hw_intf); vid_enc->hw_intf = NULL; Loading @@ -648,9 +643,9 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( * will both try to get it, depending on which is first need to call * acquire (initial), and other one needs to call get (add ref count) */ phys_enc->hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (phys_enc->hw_ctl == ERR_PTR(-ENODEV)) phys_enc->hw_ctl = sde_rm_get_ctl_path(sde_kms, ctl_idx); phys_enc->hw_ctl = sde_rm_get_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) { ret = PTR_ERR(phys_enc->hw_ctl); Loading @@ -660,10 +655,10 @@ struct sde_encoder_phys *sde_encoder_phys_vid_init( } sde_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); init_completion(&vid_enc->vblank_completion); Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +28 −39 Original line number Diff line number Diff line Loading @@ -886,22 +886,10 @@ static void sde_encoder_phys_wb_init_ops(struct sde_encoder_phys_ops *ops) /** * sde_encoder_phys_wb_init - initialize writeback encoder * @sde_kms: Pointer to SDE KMS object * @wb_idx: Writeback index * @ctl_idx: Control index * @cdm_idx: Chroma down index * @split_role: Master/slave mode * @parent: Pointer to virtual encoder * @parent_ops: Pointer to virtual encoder operations * @init: Pointer to init info structure with initialization params */ struct sde_encoder_phys *sde_encoder_phys_wb_init( struct sde_kms *sde_kms, enum sde_wb wb_idx, enum sde_ctl ctl_idx, enum sde_cdm cdm_idx, enum sde_enc_split_role split_role, struct drm_encoder *parent, struct sde_encoder_virt_ops parent_ops) struct sde_enc_phys_init_params *p) { struct sde_encoder_phys *phys_enc; struct sde_encoder_phys_wb *wb_enc; Loading @@ -921,19 +909,20 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( phys_enc = &wb_enc->base; if (sde_kms->vbif[VBIF_NRT]) { if (p->sde_kms->vbif[VBIF_NRT]) { wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_UNSECURE]; wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_NRT_SECURE]; } else { wb_enc->mmu_id[SDE_IOMMU_DOMAIN_UNSECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; wb_enc->mmu_id[SDE_IOMMU_DOMAIN_SECURE] = sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE]; p->sde_kms->mmu_id[MSM_SMMU_DOMAIN_SECURE]; } hw_mdp = sde_hw_mdptop_init(MDP_TOP, sde_kms->mmio, sde_kms->catalog); hw_mdp = sde_hw_mdptop_init(MDP_TOP, p->sde_kms->mmio, p->sde_kms->catalog); if (IS_ERR_OR_NULL(hw_mdp)) { ret = PTR_ERR(hw_mdp); SDE_ERROR("failed to init hw_top: %d\n", ret); Loading @@ -941,15 +930,15 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( } phys_enc->hw_mdptop = hw_mdp; if (wb_idx != SDE_NONE) { if (p->wb_idx != SDE_NONE) { struct sde_hw_wb *hw_wb; hw_wb = sde_hw_wb_init(wb_idx, sde_kms->mmio, sde_kms->catalog, phys_enc->hw_mdptop); hw_wb = sde_hw_wb_init(p->wb_idx, p->sde_kms->mmio, p->sde_kms->catalog, phys_enc->hw_mdptop); if (IS_ERR_OR_NULL(hw_wb)) { ret = PTR_ERR(hw_wb); SDE_ERROR("failed to init hw_wb%d: %d\n", wb_idx - WB_0, ret); p->wb_idx - WB_0, ret); goto fail_wb_init; } wb_enc->hw_wb = hw_wb; Loading @@ -959,30 +948,30 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( goto fail_wb_check; } if (cdm_idx != SDE_NONE) { if (p->cdm_idx != SDE_NONE) { struct sde_hw_cdm *hw_cdm; SDE_DEBUG("Acquiring CDM %d\n", cdm_idx - CDM_0); hw_cdm = sde_rm_acquire_cdm_path(sde_kms, cdm_idx, SDE_DEBUG("Acquiring CDM %d\n", p->cdm_idx - CDM_0); hw_cdm = sde_rm_acquire_cdm_path(p->sde_kms, p->cdm_idx, phys_enc->hw_mdptop); if (IS_ERR_OR_NULL(hw_cdm)) { ret = PTR_ERR(hw_cdm); SDE_ERROR("failed to init hw_cdm%d: %d\n", cdm_idx - CDM_0, ret); p->cdm_idx - CDM_0, ret); goto fail_cdm_init; } phys_enc->hw_cdm = hw_cdm; } if (ctl_idx != SDE_NONE) { if (p->ctl_idx != SDE_NONE) { struct sde_hw_ctl *hw_ctl; SDE_DEBUG("Acquiring CTL %d\n", ctl_idx - CTL_0); hw_ctl = sde_rm_acquire_ctl_path(sde_kms, ctl_idx); SDE_DEBUG("Acquiring CTL %d\n", p->ctl_idx - CTL_0); hw_ctl = sde_rm_acquire_ctl_path(p->sde_kms, p->ctl_idx); if (IS_ERR_OR_NULL(hw_ctl)) { ret = PTR_ERR(hw_ctl); SDE_ERROR("failed to init hw_ctl%d: %d\n", ctl_idx - CTL_0, ret); p->ctl_idx - CTL_0, ret); goto fail_ctl_init; } phys_enc->hw_ctl = hw_ctl; Loading @@ -993,13 +982,13 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( } sde_encoder_phys_wb_init_ops(&phys_enc->ops); phys_enc->parent = parent; phys_enc->parent_ops = parent_ops; phys_enc->sde_kms = sde_kms; phys_enc->split_role = split_role; phys_enc->parent = p->parent; phys_enc->parent_ops = p->parent_ops; phys_enc->sde_kms = p->sde_kms; phys_enc->split_role = p->split_role; spin_lock_init(&phys_enc->spin_lock); ret = sde_encoder_phys_wb_init_debugfs(phys_enc, sde_kms); ret = sde_encoder_phys_wb_init_debugfs(phys_enc, p->sde_kms); if (ret) { SDE_ERROR("failed to init debugfs %d\n", ret); goto fail_debugfs_init; Loading @@ -1011,10 +1000,10 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( return phys_enc; fail_debugfs_init: sde_rm_release_ctl_path(sde_kms, ctl_idx); sde_rm_release_ctl_path(p->sde_kms, p->ctl_idx); fail_ctl_init: fail_ctl_check: sde_rm_release_cdm_path(sde_kms, cdm_idx); sde_rm_release_cdm_path(p->sde_kms, p->cdm_idx); fail_cdm_init: sde_hw_wb_destroy(wb_enc->hw_wb); fail_wb_init: Loading