Loading drivers/soc/qcom/dcc_v2.c +68 −18 Original line number Diff line number Diff line Loading @@ -35,8 +35,6 @@ #define dcc_readl(drvdata, off) \ __raw_readl(drvdata->base + off) #define dcc_sram_writel(drvdata, val, off) \ __raw_writel((val), drvdata->ram_base + off) #define dcc_sram_readl(drvdata, off) \ __raw_readl(drvdata->ram_base + off) Loading Loading @@ -153,6 +151,17 @@ struct dcc_drvdata { uint8_t cti_trig; }; static int dcc_sram_writel(struct dcc_drvdata *drvdata, uint32_t val, uint32_t off) { if (unlikely(off > (drvdata->ram_size - 4))) return -EINVAL; __raw_writel((val), drvdata->ram_base + off); return 0; } static bool dcc_ready(struct dcc_drvdata *drvdata) { uint32_t val; Loading Loading @@ -252,7 +261,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) * processing the list */ link |= ((0x1 << 8) & BM(8, 14)); dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ addr = 0x00; Loading @@ -262,13 +274,21 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) } addr = DCC_RD_MOD_WR_DESCRIPTOR; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->mask, sram_offset); ret = dcc_sram_writel(drvdata, entry->mask, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->write_val, sram_offset); ret = dcc_sram_writel(drvdata, entry->write_val, sram_offset); if (ret) goto overstep; sram_offset += 4; addr = 0; break; Loading @@ -278,7 +298,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) { /* Check if we need to write link of prev entry */ if (link) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } Loading @@ -288,7 +311,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) loop |= DCC_LOOP_DESCRIPTOR; total_len += (total_len - loop_len) * loop_cnt; dcc_sram_writel(drvdata, loop, sram_offset); ret = dcc_sram_writel(drvdata, loop, sram_offset); if (ret) goto overstep; sram_offset += 4; loop_start = false; Loading Loading @@ -317,7 +343,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) * processing the list */ link |= ((0x1 << 8) & BM(8, 14)); dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ addr = 0x00; Loading @@ -340,13 +369,20 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->write_val, sram_offset); ret = dcc_sram_writel(drvdata, entry->write_val, sram_offset); if (ret) goto overstep; sram_offset += 4; addr = 0x00; link = 0; Loading @@ -370,8 +406,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) if (!prev_addr || prev_addr != addr || prev_off > off) { /* Check if we need to write prev link entry */ if (link) { dcc_sram_writel(drvdata, ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } dev_dbg(drvdata->dev, Loading @@ -379,7 +417,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) sram_offset); /* Write address */ dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ Loading Loading @@ -422,7 +463,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) link |= DCC_LINK_DESCRIPTOR; if (pos) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; link = 0; } Loading @@ -434,7 +478,9 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) } if (link) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } Loading @@ -450,13 +496,17 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) addr = (0xC105E) & BM(0, 27); addr |= DCC_ADDR_DESCRIPTOR; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; } /* Setting zero to indicate end of the list */ link = DCC_LINK_DESCRIPTOR; dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Update ram_cfg and check if the data will overstep */ Loading Loading
drivers/soc/qcom/dcc_v2.c +68 −18 Original line number Diff line number Diff line Loading @@ -35,8 +35,6 @@ #define dcc_readl(drvdata, off) \ __raw_readl(drvdata->base + off) #define dcc_sram_writel(drvdata, val, off) \ __raw_writel((val), drvdata->ram_base + off) #define dcc_sram_readl(drvdata, off) \ __raw_readl(drvdata->ram_base + off) Loading Loading @@ -153,6 +151,17 @@ struct dcc_drvdata { uint8_t cti_trig; }; static int dcc_sram_writel(struct dcc_drvdata *drvdata, uint32_t val, uint32_t off) { if (unlikely(off > (drvdata->ram_size - 4))) return -EINVAL; __raw_writel((val), drvdata->ram_base + off); return 0; } static bool dcc_ready(struct dcc_drvdata *drvdata) { uint32_t val; Loading Loading @@ -252,7 +261,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) * processing the list */ link |= ((0x1 << 8) & BM(8, 14)); dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ addr = 0x00; Loading @@ -262,13 +274,21 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) } addr = DCC_RD_MOD_WR_DESCRIPTOR; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->mask, sram_offset); ret = dcc_sram_writel(drvdata, entry->mask, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->write_val, sram_offset); ret = dcc_sram_writel(drvdata, entry->write_val, sram_offset); if (ret) goto overstep; sram_offset += 4; addr = 0; break; Loading @@ -278,7 +298,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) { /* Check if we need to write link of prev entry */ if (link) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } Loading @@ -288,7 +311,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) loop |= DCC_LOOP_DESCRIPTOR; total_len += (total_len - loop_len) * loop_cnt; dcc_sram_writel(drvdata, loop, sram_offset); ret = dcc_sram_writel(drvdata, loop, sram_offset); if (ret) goto overstep; sram_offset += 4; loop_start = false; Loading Loading @@ -317,7 +343,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) * processing the list */ link |= ((0x1 << 8) & BM(8, 14)); dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ addr = 0x00; Loading @@ -340,13 +369,20 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; dcc_sram_writel(drvdata, entry->write_val, sram_offset); ret = dcc_sram_writel(drvdata, entry->write_val, sram_offset); if (ret) goto overstep; sram_offset += 4; addr = 0x00; link = 0; Loading @@ -370,8 +406,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) if (!prev_addr || prev_addr != addr || prev_off > off) { /* Check if we need to write prev link entry */ if (link) { dcc_sram_writel(drvdata, ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } dev_dbg(drvdata->dev, Loading @@ -379,7 +417,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) sram_offset); /* Write address */ dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Reset link and prev_off */ Loading Loading @@ -422,7 +463,10 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) link |= DCC_LINK_DESCRIPTOR; if (pos) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; link = 0; } Loading @@ -434,7 +478,9 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) } if (link) { dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; } Loading @@ -450,13 +496,17 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) addr = (0xC105E) & BM(0, 27); addr |= DCC_ADDR_DESCRIPTOR; dcc_sram_writel(drvdata, addr, sram_offset); ret = dcc_sram_writel(drvdata, addr, sram_offset); if (ret) goto overstep; sram_offset += 4; } /* Setting zero to indicate end of the list */ link = DCC_LINK_DESCRIPTOR; dcc_sram_writel(drvdata, link, sram_offset); ret = dcc_sram_writel(drvdata, link, sram_offset); if (ret) goto overstep; sram_offset += 4; /* Update ram_cfg and check if the data will overstep */ Loading