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Commit 6d8ce377 authored by Giulio Benetti's avatar Giulio Benetti Committed by Greg Kroah-Hartman
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drm/sun4i: Fix dclk_set_phase 



[ Upstream commit e64b6afa98f3629d0c0c46233bbdbe8acdb56f06 ]

Phase value is not shifted before writing.

Shift left of 28 bits to fit right bits

Signed-off-by: default avatarGiulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1519836413-35023-1-git-send-email-giulio.benetti@micronovasrl.com


Signed-off-by: default avatarSasha Levin <alexander.levin@microsoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 058c84a3

drivers/gpu/drm/sun4i/sun4i_dotclock.c

+4 −1
Original line number Diff line number Diff line
@@ -129,10 +129,13 @@ static int sun4i_dclk_get_phase(struct clk_hw *hw) 
static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)

{

	struct sun4i_dclk *dclk = hw_to_dclk(hw);

	u32 val = degrees / 120;



	val <<= 28;



	regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,

			   GENMASK(29, 28),

			   degrees / 120);

			   val);



	return 0;

}